Hi team,
For the the 3.3V operation, the datasheet specifies a minimum hold time of 1.5ns but the SRCLK to QH' has minimum time of 1ns. If we are connecting output of one to the input of another, could this violate the minimum hold time at the downstream device? If so, what are other ways around this violation? Or since the upstream device must have the minimum 1.5ns hold time, the downstream is actually being held up min 1.5ns+1ns, so there won't be any violation?
Thank you,
Ishraq
The "1ns" in the minimum delay is more of a placeholder than an actual specification -- it's better than leaving it blank or putting zero, but it doesn't indicate that the device can possibly ever transition in only 1ns. Note that it's the same across the board:
Even under perfect conditions at the maximum voltage, I wouldn't expect to see a delay below 2ns -- and if that were the case, then the other device would also be operating under the same conditions, and it would be operating faster as well.
The primary concern when daisy-chaining shift registers is to make sure that you either trigger them simultaneously, which is what they were designed for, or trigger the last device in the chain first to avoid any timing issues -- this can be accomplished by either using trace length or buffers to add in delay. Usually the latter option is only needed for very large designs (think of huge signs with thousands of LEDs being controlled across several meters, for example).
