Other Parts Discussed in Thread: TMS320F280025, SN74LV4046A
We want to multiply grid frequency 32 times to be fed into TMS320F280025 microcontroller. It is desired that PLL is capable of locking grid frequencies from 47 Hz up to 63 Hz. The application circuit is shown below:
The calculations for R2,R1 and C1 are done as below:
R1 is selected to be 100 k-Ohms and the supply voltage is 5 VDC.
Fmin = 47 * 32 = 1502 Hz.
From the above graph value of C1 comes out to be around 10,000 pF.
Fmax= 63*32= 2016 ==> Fmax/Fmin = 2016/1502= 1.34.
From the below graph R2/R1=0.3. ==> R1=100K/0.3= 330K.
The filter components R3 & C2 are selected as 100 k-Ohms and 0.2 uF respectively as shown by the below calculations:
I am testing the circuit with a signal generator. It is able to lock between 50 to 61 Hz but does not lock in 47 to 50 Hz range. It is also not locking in 61 Hz to 63 Hz range. It will be nice if some one can validate the calculations and give some guidelines in fixing the frequency capture and locking ranges.