Hi team,
I received the following problem from my customer:
They are using the level shifter in the following configuration:
FPGA Pin --> (A) Level Shifter (B) --> high impedance voltage divider --> switch
All connections are direct without shunts.
Direction and enable pin of the level shifter are connected to VCCA and GND with 1 kOhm resistors.
In some cases (not reproducible) there is a LOW level before the level shifter which the FPGA cannot change and after the level shifter there is a permanent HIGH level .
Both supply voltages are stable and constant at VCCA = 1.8V and VCCB = 3.3V.
Do you have a presumption what could be the cause for this behavior?
Please let me know if any additional information is useful to solve this.
thanks in advance,
Jens
