SN74HCS74: CLR and PRESET

Hi Cedrick,

They are referring to this table in the datasheet:

Cedrick said:

The function table shows that if the CLR and PRESET pins are both active, both outputs will have a HIGH state

That is correct. Both Q and Q\ will be HIGH when CLR\ and PRE\ are held LOW at the same time.

Cedrick said:

Datasheet says this condition is unstable, does that mean as soon as the state of one input changes it will go back to operating normally?

It means that the outputs will not hold in the HIGH state for both after the CLR\ and PRE\ inputs are reverted back to the HIGH state.

When both are released simultaneously, the output state will be unknown, but one output will be the inverse of the other.

Cedrick said:

To be more specific, the preset pin will be held low, and I want the Q bar output to basically invert the signal at the reset input.
which is a normally high signal that momentary swings low at the end of every period

With the PRE\ pin held low, the Q output will be forced into the HIGH state and the Q\ output will be forced into the low state. Driving CLR\ LOW will cause the Q\ output to also go HIGH. When CLR\ is released, Q\ will go LOW again.

Cedrick said:

It should effectively act like a NOR gate right? a nor gate outputs a low for every condition except both inputs low

No - with the PRE\ input permanently grounded, the device can either output Q = HIGH and Q\ = LOW, or it can output Q=HIGH and Q\ = HIGH, depending on the state of the CLR\ pin only. In other words, the Q output is just HIGH -- it has no logic function any longer, and the Q\ output is an inverter with CLR\ as the input.

If you would like a NOR gate function, the SN74HCS02 is a good choice - or the SN74LVC1G02.

Cedrick said:

it says when both CLR and PRESET inputs are active (low), the output of both Q and Q bar is high So I want to have PRESET input tied to ground, and have the Q bar output basically invert the signal at the CLR input.

By doing this, you will have effectively turned the device into an inverter. Is there a reason you don't want to just use an inverter like SN74HCS04 or SN74LVC1G04?

Cedrick said:

I just need to know if the flip flop will go back to behaving normally as soon as the CLR input is inactive

Yes, it will behave normally when the CLR\ input is taken back to HIGH. That is to say, if PRE\ is LOW, the outputs will be forced into the "preset" states. If PRE\ is also changed to HIGH, then the device will act like a D-type flip-flop again, with the outputs holding the last known state. The only state that the device will not hold at the outputs is the "Q = HIGH, Q\ = HIGH" state, which is why there is a footnote in the function table regarding this.

Cedrick said:

what you meant by releasing both asynchronous inputs at the same time? I guess which was active last will determine the output states?

In the event that CLR\ and PRE\ are both LOW, and they are both changed to HIGH at the same time, then there is no way to know which state will remain at the output. The solution here is to just not do that.

You are correct that the last one active will determine the state, so if you intentionally release PRE\ first, then CLR\, then the output will be in the LOW state (Q = LOW, Q\ = HIGH).