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CD74HC4046A: Clarification on Output of Phase Comparator 2

Part Number: CD74HC4046A


I'm hoping to find some clarification on Figure 4 of the component datasheet (shown below).


The figure lists the following equation as the characteristic equation of the Vdemout behavior:



However, the graph shown does not match this equation.  The graph indicates that the characteristic equation is more like the following:



I'm inclined to believe the graph since the circuit as a whole operates in a 0-Vcc range, but I'd like to be sure instead of making assumptions.  Any thoughts on this apparent discrepancy?  Thank you

  • Hi Kyle,

    I agree with your assessment -- the equation for the PC2 filtered output should be:

    VDEMOUT = (VCC/4π) (φSIGIN - φCOMPIN) + (VCC/2)

    The PC2 signal (average) will swing from VCC when the rising edges are +2π out of sync to 0V with the rising edges -2π out of sync.

    I'll make a note to fix this in the next datasheet revision -- and to check our other '4046 functions to  see if that error propagated across.


    If you haven't found it already - this app note may be interesting / helpful to you: Implementation of FSK Modulation and Demodulation using CD74HC4046A