SN74LVC3G17: Voltage drop in input supply VCC while giving input signal

Hello Praveen,

Are you saying that the voltage at the VCC pin is getting pulled down or are you saying the output voltage is getting pulled down (or maybe both)?

When the device is not switching, is the VCC stable at 3.3V?

If so, it is possible that when the device is switching at the higher frequency, the output is switching fast enough and drawing enough RMS current that is loading down the VCC and the VCC is setting down to 3.3V based on what looks like is an LC filter you have at the connection of the VCC. 

If you bypass the inductor (ferrite bead?) does this make it so that the VCC is more stable at a higher voltage? 

It may also depend on how current the output is supplying to the CCD. Do you know if this is a high current load? What is the load?

If so a combination of the switching frequency and the high output load could drag the supply down and the LC filter doesn't have enough time to recover to the 3.3V and is settling closer to 3.0V. 

To test the LC theory, you could measure the VCC on both sides of the inductor. Is the supply itself getting pulled down to 3.0V or is it just the VCC line that is? If its just the VCC line then that would seem to confirm the LC filter loading theory.

Best,
Michael

Hello Michael J Schultis

Are you saying that the voltage at the VCC pin is getting pulled down or are you saying the output voltage is getting pulled down (or maybe both)?

-- VCC pin getting pulled down. 

When the device is not switching, is the VCC stable at 3.3V?

-- Yes. The voltage is stable. 

If you bypass the inductor (ferrite bead?) does this make it so that the VCC is more stable at a higher voltage? 

-- Yes, We bypassed a FB, Even we an able to see a drop at VCC. (FB part number: BLM18EG221SN1D)

It may also depend on how current the output is supplying to the CCD. Do you know if this is a high current load? What is the load?

-- It's a CCD image sensor clock line. we are driving a 4meter cable. 

Even we bypass the inductor we could able to see the loading happening in the VCC supply of buffer. 

Also, the supply of the buffer is given by a variable power supply circuit. 

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Transistor Emitter is connected to the buffer, (Transistor part number: KSC3265YMTF)

VR2 is used to control the buffer voltage. What might be the reason for this buffer VCC drop? 

With three 27 MHz input signals, the dynamic power consumption is 19 pF × (3.3 V)² × 27 MHz × 3 ≈ 16.8 mA. In addition to that, you have the power consumption of the load (the 4 m cable), which might be even larger. (See [FAQ] How do I Calculate Power Consumption or Current Consumption for my CMOS Logic Device?)

Do you get the same drop when the device is not not switching and you add a 100 Ω load resistor? Does disconnecting the cable decrease the drop?

Hello Clemens 

We have supplied a power supply from the fixed regulator. During that time we absorbed the total current is about 30mA. 

Do you get the same drop when the device is not switching and you add a 100 Ω load resistor? Does disconnecting the cable decrease the drop?

Yes, While checking with 0 - 500ohm(Using Pot) load, We absorbed a load change of about ~100mV. 

Also, we have a doubt about logic circuits like LVC, HC, HCT will make a difference?

As you have seen, that power supply circuit has bad load regulation. Consider using an integrated regulator like the TLV741P or TLV713P.

Different logic families have different power consumption. But a weaker family like HC might not be able to drive 27 MHz on a 4 m cable.

Also, we have tried different power supplies like 5V @ 2A regulator input. Still, we could find the loading issue, 

Will you please suggest to me, driver, for 27Mhz @ 4m cables?

Also, I like to know if parallelizing the two buffers will help in this loading issue.?

For 27 MHz over 4 m, a single-ended signals is not a good idea. I would use a differential signal, i.e., LVDS.

Hi Albert Xu1

- Use only one channel instead of shorting all three channels together.

To improve the drive strength we have shorted all three channels. (This a main reason for shorting all three channels together)

- Increasing the bypass capacitor

Yes, We tried this by adding 100uF But did not help us. 

- Increasing the load resistor

It's a CCD sensor clock signal, If I increase the load resistor it will definitely affect the signal quality. (This will reflect in the image quality also)

Right now I am trying to parallelize the two buffers. To improve the Drive strength once done I will share the result.  

Hi Clemens 

The CCD sensor that we have single-ended. So we could not use a differential pair. (Sensor is suggested by the client so we could not able to change)

If you cannot change the cable, then you have to use as many buffers in parallel as necessary. Consider the SN74LVC541A.

To prevent the supply voltage drop, use a proper regulator, and good decoupling near the device.

Hi Clemens 

I like to know any input impedance for 74LVC3G17 is specified otherwise if I connect the series buffer will help with the loading issue.  

If any chance if I increase the input signal drive current strength for (27Mhz) will help in the loading issue.  

The input impedance of LVC devices is several GΩ.
The output impedance of LVC devices is typically 12 Ω.

To increase the drive strength, use multiple outputs in parallel. But this is completely independent from the VCC drop.

Thanks, Clemens 

I tried to do parallelize the two buffers but it not help full. Still, I am facing a loading issue. 

I like to know there is any minor difference between ACT, HC, and LVC logic technology according to the drive capability? 

Which is better to go in the future? To drive the 4m cable (27Mhz). 

AC is not any stronger than LVC. HC has much weaker outputs.

You could try a fast gate driver like the LM5114, but at 27 MHz, it might overheat.

There is no good solution to drive a single-ended 4 m cable with 27 MHz. This is why I suggested LVDS. What prevents you from putting an LVDS receiver at the other end?

Hi Clemens 

Thanks a lot, I will check once and let you know. 

Hi Clemens

Still, I have some confusion over this. 

I just connected a 100 Ohm resistor in output as a load. Without connecting the Sensor cable. Most probably the load current will be around 50mA.

I tried to do parallelize the two buffers. Still, I am facing a loading issue. This is how? SN74LVC can supply 50mA independently. 

As of now, I have just eliminated the 4m cable.

Even it is connected in parallel it could not able to drive a 50mA (100 Ohm load)? Why it is happening like this? 

What exactly do you mean with "loading issue"? A drop of VCC, or of the output voltage? How large?

A single LVC output has an impedance of about 12 Ω. You can reduce this by paralleling outputs, or by using a stronger device (like the gate driver I mentioned).

The loading issue is we did not get sufficient current drive strength.

Because, of that, an Input voltage Vcc drops around 50mV to 300mV.  

Yes, We also looking into gate driver. 

The best way I've found to drive a transmission line with a logic gate is to use a source termination to match the line impedance as closely as possible.

As Clemens said, the LVC output impedance is 12 ohms -- if you are using a 50 ohm t-line, then you can add 38 ohms to get the best response possible from the logic gate (using only one channel). Adding more channels in parallel will only reduce the impedance further and cause a worse mismatch -- I don't see any case where that would improve the received signal integrity at the receiver.

Additionally, parallelling more channels will also add more supply current requirement, which is likely the cause of your supply droop.

I have an FAQ that goes into some details on the usage of transmission lines with logic located here: [FAQ] What happens when I connect a logic device's output to a 50 ohm transmission line? 

Hi Emrys Maier 

Thanks a lot for a great explanation. 

But I have one doubt. We referred to the circuit which is provided by our client. There they are using a similar kind of buffer circuit and it is working well enough without a drive issue.

Please find the image. 

Part Number: TC74HC14AF - Datasheet attached below. 

TC74HC14AF_datasheet_en_20160921 (3).pdf

For them, the circuit is working fine without any driving issue. Input VCC is more stable. 

I have big confusion, how is working for them with HC logic without drive issue. Even LVC is better than HC logic. 

Please find the buffer schematic for your reference. 

Compare buffer..pdf

A HC output has an impedance of about 30 Ω. So to get the same effect as two HC outputs in parallel, a single LVC output is about right.

Please note that that circuit uses a 47 µF capacitor.

Hi Clemens, 

Yes, Capacitor we have tried with 100uF. Not helped. 

Hi Emrys Maier

Even my buffer input signal voltage is 3.3V, It just a DC high. (Not 27Mhz signal) - No Load Condition

In this condition also buffer voltage VCC is dropped around 50mV.  

Even my buffer input signal voltage is 3.3V, It just a DC high. (Not 27Mhz signal) - No Load Condition

In this condition also buffer voltage VCC is dropped around 50mV.  

50 mV compared to what? In what other case is VCC 50 mV higher?

I am giving high input to buffer SN74LVC3G17 around 3.3V (Input Voltage)

Without input voltage the Supply voltage VCC is stable at 3.3V. Once I give 3.3V input as a signal to the buffer. 

The Supply voltage drops to 3.2V.

Does "without input" mean a low voltage? Or a floating input?

Is there any load on the output, or some pull-down resistor, or anything else that loads the supply?

Does "without input" mean a low voltage? Or a floating input? Yes, It's a floating pin. 

Input pins should never float; this is likely to generate cross currents and increase the power consumption.

Can you measure how much current flows out of the supply? The SN47LVC3G17 itself should not consume any noticeable amount.

Hi Clemens, Yes I will check on that. 

Hi Clemens, I forget to convey one thing, we will change the buffer voltage (VCC) - (3.3V to 4.5V), Using a Variable regulator. 

We will fix the voltage of the buffer once we get the proper image data. ( VCC voltage might be 3.3V or 3.8V or even 4.2V) This changes according to the image sensor. 

So, I have doubt,

This voltage change affects the dynamic performance of LVC logic buffers. 

Like with any CMOS device, the output impedance slightly decreases with increasing supply voltage.

If you want to replicate the TC74HC14AF solution, just use the SN74HC14, SN74HCS14, or SN74AHC14.

Hi Clemens

Thanks, We will check on that. 

Hi Clemens 

I like to know, When the rise and fall times of the input signal are small (a few ns), It's any dynamic supply current of the buffer differ? 

If I reduce the rise and fall time of the buffer input signal. This would help to solve the driving issue? 

Also, I like to know the Delta ICC? Do I need to consider this? 

Slow edges at the inputs increase cross currents, but will not affect the output.

ΔI_CC applies only to input signals that are lower than the supply.

Yes, In our case. The input signal is lower than the supply voltage. 

Then you need a level shifter. What is the input voltage? Does it go down to 0 V?

We will use signal input 3.3V (27Mhz)

Input power supply VCC is 3.5V to 4.5V.  

Then use a shifter like the SN74LV1T34. (Its drive strength is similar to (A)HC.)

Sure, I will check. 

Hi Clemens,

Also, I like to know how the input signal will affect the ΔICC.  

How Icc will affect it when the input signal is lower than supply VCC?