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SN74LVC16T245: Data rate questions - FPGA 2.5V to 1.8V translation

Part Number: SN74LVC16T245
Other Parts Discussed in Thread: SN74LVC827A, SN74AUC16244, SN74AUC244, SN74AUCH16244, SN74AUCH244

My customer request to translate 10 bits from 2.5V FPGA to 1.8V,

I suggest the SN74LVC16T245 due to >100Mbps data rate, assuming I can leave the extra 6 bits unused.

in total, there is 1 clock bit at 100MHz and 9 data bits (under 100MHz) 

questions are:

in SN74LVC16T245 

1. assuming my clock is 100MHz, do the other inputs need to share the remaining100Mbps? or are the other bits forced to operate at 100MHz?

2  do all input bits change at the maximum data rate?

another option I suggested was  SN74LVC827A 10 bit buffer, for which I would ask the same questions, and in addition: will SN74LVC827A support 2.5V --> 1.8V at 150MHz?


 

  • All channels are independent. The propagation delay for each input/output pair is measured as tpd.

    LVC at 1.8 V might not be fast enough for 100 MHz. Better use an AUC device like the SN74AUC16244. (For unidirectional downtranslation, you can simply use a buffer with overvoltage-tolerant inputs.)

  • Ok, thanks for clarifying this.

    for SN74AUC16244DGVR, is there any app note explaining what to do with recommend bypass capacitance for VCC pins?

  • Regarding the SN74AUC16244DGVR, the raise/fall time is 20nS/V.
    Can you recommend a buffer with Tr/Tf of 5nS/V or less? Some of our signals are very short and with Tr/Tf of 2nS


  • Regarding the SN74AUC16244DGVR, the raise/fall time is 20nS/V.

    I'm not sure exactly where the confusion is here.

    You are referring to the _maximum_ recommended input transition rate:

    Maximum means that the input transition rate can be less than this, down to 0 ns/V.

    -

    The output transition rate is not the input transition rate. It is not specified in the datasheet, however this device has very low delays, which include the transition time:

    At 1.8V operation, the delay from input to output is only 1.8ns, which indicates that the rise time to 50% is much less than 1.8ns. For these devices, you should expect transitions closer to 0.5ns/V.

  • Thanks. I got it.

    Few more questions:
    1. Do you have any recommendation for using PU/PD resistors in the inputs  to avoid possible floating stage and over heating of the device (SN74AUC16244DGVR) as a result?
    2. Bypassing capacitors of 100nF are sufficient (per VCC pin)?
    3. And if there are any layout recommendations that you can share?


  • 1. Do you have any recommendation for using PU/PD resistors in the inputs  to avoid possible floating stage and over heating of the device (SN74AUC16244DGVR) as a result?

    Yes, the inputs should not be left floating. If your system cannot guarantee that the inputs are at a defined value at all times that the supply is on, then I would recommend using 10kΩ pull-down resistors to ensure that the inputs are defined.

    [FAQ] How does a slow or floating input affect a CMOS device?

    [FAQ] How do I terminate any unused channels of a logic device?

    2. Bypassing capacitors of 100nF are sufficient (per VCC pin)?

    Since this device has multiple supply pins, my recommendation would be to use a 10nF (0.01uF) or 22nF (0.022uF) capacitor on each supply pin. This would be 4 total capacitors for this device.

    [FAQ] How do I select a bypass capacitor for a CMOS logic device?

    3. And if there are any layout recommendations that you can share?

    The only specific layout restriction/requirement for this device is to keep the bypass capacitors electrically close to the supply pins.

  • Regarding the 10Kohm PD resistors, if I'm using only 8 buffer (3OE and 4OE are connected to GND), the inputs of 3Ax and 4Ax can be directly connected to GND (saving PCB space) , or PD is also recommended in this case? 

  • Unused inputs can be connected directly to GND (or VCC). You would need a pull-down/-up only if you wanted to change the input voltage during debugging.

    If you're using only eight channels, consider the smaller SN74AUC244.

    If you do not have pull-up/-down resistors on any of the signals that you are actually using, then you can save the PDs on the unused inputs by using a device with bus-hold inputs, SN74AUCH16244 or SN74AUCH244.