SN74HCU04: Input capacitance in linear biasing

Hi Cedrick,

I'm afraid that's not something that we characterize for this device.

The input capacitance given in the datasheet was most likely measured under typical operating conditions, zero bias at the input and using a 10 MHz signal for measurement. I can't be entirely sure since it was done so long ago, but this is a common method we use.

Assuming this is correct, the input FETs are in the saturation region of operation, and thus will be operating at approximately 2/3 of the "total gate capacitance" -- and when the device is biased as you have described, the FETs will be in the non-saturation region of operation, and thus will be expected to be 1/2 of the "total gate capacitance." The book I'm paraphrasing here is "CMOS LOGIC CIRCUIT DESIGN" by John P. Uyemura, p 27. 

So, given that the HCU04 typical input capacitance is 3pF (from the DS), we can calculate the linear region capacitance to typically be about 2.25pF, which I would round to 2pF since these values won't be all that accurate.

All MOSFETs have this effect: en.wikipedia.org/wiki/Capacitance-voltage_profiling#C-V_characteristics_metal-oxide-semiconductor_structure. But it happens only at low frequencies (red curve), so it does not matter for most logic devices.

I expect the CD and SN devices to behave pretty much identically, i.e., they can replace each other.

If you are designing a new board, consider a device like the SN74LVC1GX04 instead.