This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TXB0102: Port impedance of Voltage Level Translator (TXS0102/TXB0102/LSF0102)

Part Number: TXB0102
Other Parts Discussed in Thread: TXS0102, LSF0102

Regarding the Voltage Level Translator  (TXS0102 / TXB0102 / LSF0102) ,

in case supply voltage is supplied to the VccB(or Vref_B) port and is not supplied to the VccA(or Vref_A) port (= 0V),

if the enable port (OE or EN) is set to Low level input voltage, will port B1 and B2 be in the Hi-impedance state?

  • Hello Kazuya-san,

    All of these devices will have all pins in the high-impedance state in the described condition.

    The LSF device is a bit different since it is not a buffered device - when the shared gate (EN) pin is held at 0V, then all channels will be disabled (cutoff mode). It's important to note that this should be done via an open-drain connection, as the EN pin in the LSF is a vital component in the bias circuitry, and driving it "high" would also disable the device's translation capability.

  • Thank you for your support.


    Please let me know just in case.


    For TXS and TXB devices, I understand that A port is in a high impedance state under the condition you marked it in yellow,
    but is B port also in a high impedance state?

  • The datasheet is unclear -- we will have to wait for the applications team that supports this team to come back to the office (next week), at which time they should be able to answer.