Other Parts Discussed in Thread: SN74HCS74
Dear team,
We are working on D-flipflop, but it gets triggered on both rising and falling edges. (From datasheet it is observed that CLK should trigger on rising edge only).
We are providing 2.85V at VCC, PRE, 1D and 2.9V at 1CLK with 0.2Hz frequency.

In this image Yellow signal is 1CLK and Green signal is Output (1Q).
Regards
Abhay Tyagi
