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[FAQ] Why is there a voltage offset at the input of the SN74AXCxTxxx device?

FAQ: Logic and Voltage Translation > Voltage Translators >> Current FAQ

The AXC family of Voltage Translators have built in dynamic pull-downs at the I/O. These pull-downs assist with with the glitch free power sequencing feature included in this family.

The pull-downs were designed to be weak as to not contend with any CMOS driver connected to the I/O. However, when a weak pull-up is added to the I/O it can create a voltage division.

If there is a need to have pull-ups connected to the I/O of an AXC translator, it is recommended to keep the value below 30 kΩ.