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LSF0108-Q1: VREF_B decoupling capacitor size

Part Number: LSF0108-Q1

Hi,

The datasheet recommends C at VREF_B with 100 nF. That limits LOW->HIGH slope speed on EN to many milliseconds.

Somewhere else in some video info I found:

"The 0.1 microfarad capacitor connected to the VREF B voltage node provides a path to ground for high frequency noise. While it is not required for operation, it is highly recommended."

What is a recommended minimum capacitor size? When is it possible to remove it completely?

I would love to get some guidance on the capacitor size WITH some background for the arguments.

Thank you.

  • Hi Holger,

    Please note that 100nF is also equivalent to 0.1uF. 

    What is a recommended minimum capacitor size? When is it possible to remove it completely?

    Up to 10nF are some min typical values observed in various applications. It is also possible to remove it if noise and a smoother output are of no concern.

    I would love to get some guidance on the capacitor size WITH some background for the arguments

    Please see [FAQ] How do I select a bypass capacitor for a CMOS logic device? to help with the sizing as well as providing further background, thanks.

    Best Regards,

    Michael.

  • Obvious that 0.1u == 100n, but thanks for that reminder. Slight smile

    As for the link to the bypass capacitor selection: The capacitor on VREF_B is connected to the gates of the internal FETs and suits a different need than a typical bypass capacitor.

    If 10 nF is ok for this use case, thanks for that input

  • Hi Holger,

    Apologies for the misinterpretation as I misunderstood your statement for the 100nF and 0.1nF as discrepancies between the datasheet and the training video.

    Please also note that the 100nF - 10nF recommendation is for the power supply pins (and as close as possible) similar to the FAQ and the datasheet/training videos, thanks.

    Best Regards,

    Michael.

  • VREF_B is not a power supply pin in traditional means for the LSF.

    The capacitor is to buffer EN voltage level (gate voltage of all FETs) to be stable. 

    I see that there is no clear guidance on how much buffer is needed there.

    We will check in electrical validation which value still properly fulfils our requirements.

  • Hi Holger,

    That is correct, while also case by case per the system/application.

    My understanding is that you are trying to reduce the time it will take to transition and would suggest to keep going even as low as a 0.1nF while also observing the offset / noise you are willing to work with, thanks.

    Best Regards,

    Michael.