SN74LVC2G126: Output Rise/Fall Times

At 1.8 V, LVS can do 80 MHz.

See [FAQ] What is the output transition rate for a logic device?

At 1.8 V, AUC family devices like the SN74AUC2G126 work much better than LVC. (Please note that AUC outputs change impedance during transitions, so the rise/fall time cannot be easily estimated as in the FAQ; see the AUC application report.)

Hi Darren,

We don't specify jitter for standard logic buffers -- for this type of specification, you will have to switch to a clock buffer.

I agree with Clemens -- while the LVC can handle 66.66MHz, I would not recommend it as my first solution. The AUC family is much better at 1.8V.

That calculation does not apply to AUC outputs; see the AUC application report.

Why do you care about the rise/fall time? If the propagation delay is smaller than the period, it will definitely work.

AUC also works at 2.5 V.

Hey Darren,

With a typical load, the rise time for an AUC device will be under 1ns. These are the fastest devices in the logic portfolio.

Darren (FAE) said:

Do we have any data for the following conditions?

No, I'm afraid not. Rise and fall times were not part of the specification or characterization of the device -- if they were, they would be in the datasheet.

Darren (FAE) said:

I expect the output Tr/Tf to be independent of the input Tr/Tf, yes?
(A logic buffer is not an amplifier; output is triggered when input passes a certain threshold)

Yes, this is true, however a slow input can cause erratic behavior which will affect the output signal. All CMOS inputs need to meet the datasheet requirements:

From the application report Application of the Texas Instruments AUC Sub-1-V Little Logic Devices 

Darren (FAE) said:

I read through your blog post and did some math.
I think I have a pretty good understanding of the process (t = -RC*ln(1 - dV))
Can you check my math (excel)
I was getting <200ns for LVC at 3.3V and ~300ns for AUC at 1.8V.
(CL = 15pF and 35%~65%Vcc = dV = 0.3) These numbers use MAX rds(on) so are really kind of worst-case?

I think you're off by a factor of 1000 (I did not check your excel). For 10% to 90%, you can use the easy equation: t_t = 2.2 * R * C

With CL = 15pF and an LVC device (about 13 ohms), the rise time is calculated as  approximately195 ps.

As Clemens mentioned, the AUC device has a variable output impedance, so this type of calculation won't work very well with it.

-

From the same application report I linked earlier, there's a waveform for driving a transmission line from an AUC family device at 1.8V:

As you can see, the edges are extremely fast. The AUC family easily drives 125 MHz signals.

If you have calculated 0.3 ns with the DC resistance, then the actual rise/fall time (where the output impedance is much lower) will certainly be below your limit.

CMOS devices are designed to have symmetrical outputs. But the remaining skew is neither specified nor guaranteed.