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SN74HC573A-Q1: Output probabilistic fault at the power up

Songzhen Guo
Intellectual 2770 points
Part Number: SN74HC573A-Q1

Hi Experts,.

SN74HC573A-Q1 is used  in customer for BMS. The project is under DV. There is fault output of SN74HC573A-Q1, it will cause the whole system down.

This device need be fixed before 9/10. So it can catch the PV test progress.

Here is the description for this issue：

When the power up, the LE and /OE are pulled down, the input(D) is low,  but sometimes the output is high. we find that before the power up, the power pin is 0.8V, it's cause by the MCU. Our competitor who  have a same device doesn't have this issue. Could you help to explain this issue? thanks.

The datasheet of SN74HC573A-Q1 is described that the /OE need keep high before the power up, but in this system, it can't  meet this requirement. Because if they pull up the /OE, the PCB need redesign and our device can't catch the PV timeline.  I also let customer to do the test in current board(Fly a line between 5V and /OE and SN74HC573A-Q1 is powered by 5V), it also has a power sequence for /OE and 5V, it can cause the fault output. When the software power down the OE, the output is still high. It also need pull up LE and pull down D1, in that time, Q1 is pull down with D1. But the initial will fault before software pull up LE. Could you also help to explain this? Why the Q1 is high output when /OE is pull down? thanks.

Best Regards

Songzhen Guo

  • 0
    Guru 243820 points

    [FAQ] What is the default output of a latched device? says:

    Flip-flops, latches, and registers do not have a default state on power up.  The output is in an 'unknown' state until data is clocked through. […]

    Due to imperfections in manufacturing and system loading, it is possible for a latch to appear to start the same way every time, even when tested many times. It is important to note that this does not guarantee that the output will always be that value. Different devices can have different imperfections that can result in a different "default" output state, and this state can be changed by system loading.

    This applies also to the devices made by onsemi and Nexperia.

  • 0
    TI__Guru* 96591 points

    Hi Songzhen,

    As Clemens pointed out, the startup state of a latch is unknown.

    From the datasheet:

    The expected output in the described state is Q0, which is the previous state. Since this is happening at power-up, the "previous state" is "unknown" and the output can start either high or low - this is random.

    It is common to see these outputs start in one state far more often - for example, the low state, but that is not any guarantee that it will happen that way every time. The system must initialize any latched device before starting operation.