Other Parts Discussed in Thread: TXU0101, TXU0104, SN74AHC1G125
Hi Team,
Our customer is using a controller and two responders with SPI interface and would like to clarify about the connections of the SPI pins. According to our customer,
I am designing a circuit that uses TXU0304 chips to level shift SPI bus signals to multiple SPI peripherals. Each peripheral has a separate TXU0304 chip, and is connected to a single SPI master. Each SPI peripheral puts the MISO signal in a high-impedance state when the CS signal is de-asserted. My question is, how should I handle the MISO outputs of the TXU0304 chips to the SPI master? Do I need to use the OE pin on the TXU0304 to put all outputs in high-impedance state when the respective SPI CS signal is de-asserted? Could I just tie the OE pin to CS? Is there a recommended approach for this type of topology?
He also added,
Attached is my schematic at the moment. I'm concerned that although the MISO pin on each SPI device is put in high-impedance when CS is de-asserted, the A4Y pin on the corresponding TXU0304 chip will not be in high-impedance, resulting in bus contention. Is this the case? Should I route a GPIO pin to the OE pin on each TXU0304 to force it to high-impedance when CS is de-asserted?
I understand that in multiple SPI devices, each CS pin should be connected to an individual I/O of the controller. It seems that a better configuration is to connect the SCK, MOSI, MISO of U3 and U4 in parallel, remove U2 and add a TXU0101 for another CS pin from the controller to CS of U4?
Alternatively, using two TXU0304 as shown in the diagram above, connecting the BY1 of U1 to an inverter then to OE of U1 (the same configuration with U2) and separating A1 of both U1 and U2 will prevent data collision between the MISO of U3 and U4.
Can you please confirm which solution will work?
Regards,
Danilo