FAQ: Logic and Voltage Translation > Quality and Manufacturing >> Current FAQ
This is provided as information only, and is not a guarantee of device performance under the conditions described. This is not a Pin FMEA document, as Standard Logic devices are not rated for "Functional Safety". For Functional safety devices, see ti.com/functionalsafety
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide adequate design and operating safeguards.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide adequate design and operating safeguards.
-
Table 1. Failure effect definitions
| Class | Failure Effects |
| A | Potential device damage that affects functionality |
| B | No device damage, but loss of functionality |
| C | No device damage, but performance degradation |
| D | No device damage, no impact to functionality or performance |
-
Table 2. Analysis for pin short-circuit to GND
| Pin Name | Description of Potential Failure Effect(s) | Failure Effect Class |
| Input | Input pin functionality is defined such as input is LOW - See Device Function Table (For example, if buffer input is GND, output will always be driven LOW) |
B |
| Output | Can cause excessive output current, output will not switch (For example, if buffer output is shorted to ground and is attempting to drive to VCC) |
A |
| VCC | Device will not be powered, because short is external to device System level damage may occur in this scenario |
B |
| GND | Normal operation | D |
-
Table 3. Analysis for pin open-circuit
| Pin Name | Description of Potential Failure Effect(s) | Failure Effect Class |
| Input | Pin is floating, can change output state and cause excessive current from VCC to GND See Implications of Slow or Floating CMOS Inputs - ti.com/lit/scba004 |
A |
| Output | Normal operation | D |
| VCC | Device will not be powered | B |
| GND | Device will not be powered | B |
-
Table 4. Analysis for pin short-circuit to VCC
| Pin Name | Description of Potential Failure Effect(s) | Failure Effect Class |
| Input | Input pin functionality is defined such as input is HIGH - See Device Function Table (For example, if buffer input is VCC, output will always be driven HIGH) |
B |
| Output | Can cause excessive output current, output will not switch (For example, if buffer output is shorted to VCC and is attempting to drive to GND) |
A |
| VCC | Normal operation | D |
| GND | Device will not be powered, because short is external to device System level damage may occur in this scenario |
B |
-
Table 5. Analysis for pin short-circuit to next higher pin number
| Pin Name | Shorted to | Description of Potential Failure Effect(s) | Failure Effect Class |
| Input | Input | Two inputs shorted together will not cause damage unless there is external bus contention that drives the input such that VIL<Input Voltage<VIH in which case excessive supply current to gnd may cause damage System level damage may occur in this scenario |
A |
| Input | Output | Can cause excessive output current, output will not switch (For example, if inverter input is shorted to output) |
A |
| Output | Output | Can cause excessive output current, output will not switch (For example, if one output is driving to VCC and another output is driving to GND) |
A |
| GND | VCC | Device will not be powered, because short is external to device System level damage may occur in this scenario |
B |
| NC | Any Pin | A No Connect connected to any pin will not cause damage to the device, as No Connect pins have no internal connection. | D |
| DNU | Any Pin | A Do Not Use connected to any pin may cause damage to the device. | A |