LSF0108-Q1: The high level output voltage of A side is clamped by VrefA

chaodong deng

Part Number: LSF0108-Q1
Other Parts Discussed in Thread: LSF0108,

Hi Ti support team,

We encountered one issue when using LSF0108-Q1 level shifter. Below is the schematic. We connected VrefA to 1.2V source. VerfB and EN are tied to 3.3V source through one 100 kohms resistor. The signal for A side to B side is ok. But we met issue when translating signal from B side to A side. In our case, A side ports are connected to a FPGA whose VDDIO can be either 1.8V or 2.5V or 3.3V. But B side ports are connected to a fixed 3.3V DUT. For bidirectional pins such as SDA, translation from A side to B side is ok. But when signal direction is reversed, if B side input and high level signal, A side output will be clamped at VrefA which is 1.2V. But we have a pull up the pins to the VDDIO of FPGA. What we expect is that the high level output of A side should depends on the pull-up source. We have watched the video of LSF family level shifter. We think that the A side output high level voltage shouldn't be clamped by VrefA according to the structure of LSF0108 as below picture shown. Do you have any idea about this issue? Thanks!

thanks and best regards,

chaodong

over 1 year ago

0 Clemens Ladisch over 1 year ago

Guru 243910 points

You are correct that the A-side voltage should be determined by the pull-up resistors.

Something sinks the current through the pull-up resistors. Are there any pull-down resistors, or any other load, on the A side?

0 chaodong deng over 1 year ago in reply to Clemens Ladisch

Prodigy 50 points

Hi Clemens,

There is no pull down resistors. And the load is the other LSF0108 A ports. The whole setup is as below. Thanks!

thanks and best regards,

chaodong

0 Clemens Ladisch over 1 year ago in reply to chaodong deng

Guru 243910 points

In this image, the signals at the A pins are pulled up to 1.8 V. So the high-level voltage is expected to be 1.8 V.

At both B pins (FPGA and DUT2), the signal is pulled up to 3.3 V. Is it that what you measure there?

0 chaodong deng over 1 year ago in reply to Clemens Ladisch

Prodigy 50 points

Hi Clemens,

We measured at the pin of LSF0108 A port pins directly. We also expect that the high-level voltage should be 1.8V. It works in the previous setup. But when we change the setup as below, we change the pull-up source of A ports to a supply higher than VerfA. The high-level output will be clamped by VrefA. Thanks!

thanks and best regards,

chaodong

0 Clemens Ladisch over 1 year ago in reply to chaodong deng

Guru 243910 points

If the A pins are at 1.8 V, then a current is sourced by VDDIO_3.3V, flows through the pull-up resistors, and then is sunk somewhere. This schematic does not show any place where this current can be sunk.

Is the voltage at both B pins correct? Do VrefA and VrefB have the correct voltage (VrefB should be about 0.6 V higher than VrefA)?

0 chaodong deng over 1 year ago in reply to Clemens Ladisch

Prodigy 50 points

Hi Clemens,

The voltage on B side is correct. You can see in the schematic that VrefB is about 1.6V higher than VrefA for both two LSF0108. We are also confused about where the current goes to. Do you have any idea about that? Thanks!

thanks and best regards,

chaodong

+1 Clemens Ladisch over 1 year ago in reply to chaodong deng

Guru 243910 points

There is no obvious explanation. DUT#1 could pull the line low, or there could be a solder bridge somewhere, or the LSF pinout is not correct.

Would it be possible to measure how much current flows out of VrefA?

0 Michael Ikwuyum over 1 year ago in reply to chaodong deng

TI__Mastermind 22275 points

Hi Chaodong,

In addition, please see LSF0108-Q1: The output voltage of A side is limited by VrefA.

Also, could you help confirm the data rate frequency of the lines not pulling high? Thanks.

Best Regards,

Michael.

0 chaodong deng over 1 year ago in reply to Clemens Ladisch

Prodigy 50 points

Hi Clemens,

We have found out the current sunk. A resistor is accidentally connected to port A during rework. Thanks for your help.

thanks and best regards,

chaodong

0 chaodong deng over 1 year ago in reply to Michael Ikwuyum

Prodigy 50 points

Hi Michael,

Thanks for your help. We have found out the reason.

thanks and best regards,

chaodong

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LSF0108-Q1: The high level output voltage of A side is clamped by VrefA