SN74HCS74: Clock edge issue

The output signal of a digital gate always has fast edges.

The '132 device has Schmitt-trigger inputs, the '00 has not. So there is a problem with the input signal of that gate. Which you have not shown in the schematic.

Thanks for your reply!

Here is my schematic

The signal RTCINT is an output of  RTC alarm interrupt,GH1248 is a magntic switch IC which outputs low level when actived.

The signal PWRCON comes from an MCU pin.

Clemens Ladisch said:

When PWRCON changes, the rising edge of the signal at the B input of U5 will be very slow because the voltage is pulled up weakly through R4. (The falling edge might also be slow because of R6.) This will lead to oscillations if U5 does not have Schmitt-trigger inputs.

Hi,Clemens,

I can see what you mean ,the slow edge input signal could cause the abnormal clock signal output. 

However there's something I can't understand yet.Below are the signal waveforms of SN74HCS74.

 The yellow signal is clock,the green signal is Q~。

The waveform of clock signal looks fine from the screenshot,and the output of SN74HCS74 still changed on the falling edge clock signal.

Thanks for your patience !

The waveform of clock signal testified your opinion.

Appreciate your help!!