SN74LVC16245A: PSpice model

Hello Masa-san,

Choosing a damping resistor is not typically a SPICE simulation activity - they should be doing that with a signal integrity (SI) simulator using IBIS models (much more accurate than using our SPICE models). The SPICE model will not account for transmission line effects and output parasitics of the device, which are the primary reasons to add a damping resistor.

It's actually quite simple to select a damping resistor -- I would consider simulation 'overkill' unless they have a very complicated transmission line geometry. They just need to know the characteristic impedance of the traces being used (typically Z₀ = 50 Ω) and the output impedance of the driver device (For LVC at 3.3-V supply, R_O ~= 12 ohms, calculated from the datasheet values). The equation for the damping resistor is:

R_d = Z₀ - R_O

So, in the case provided here, the damping resistor would be 38 ohms. Usually getting close is fine for this type of impedance matching on digital signals, so a typical 33 Ω resistor would work well.

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The absolute best way to choose these is to first estimate the value as I did above, then measure the signals in the prototyping stage and update the values to give the best results.

Hello Emrys-san,

Sorry for the late reply. And Thanks for the suggestion.

Unfortunately, the Behavior model you created does not output from B even if a signal is inserted into A.

Regards,

Masa

Thanks for letting me know, I will look into that issue.

Hello Masa-san,

Masakazu Adachi said:

In the configuration shown in the attached figure, how should the damping resistance be calculated? Is it OK to calculate Z0_1 and Z0_2 and adopt either one with higher resistance value?

Only one trace can be matched with a damping resistor because each branch creates reflections that will be seen at the other branch.

The best approach for signal integrity would be to separate the branches, buffer and match each independent line:

I found the issue and fixed it in this version of the model:

8726.SN74LVTH16245A.CIR

The control logic for the B channel was inverted.

Hello Emrys-san,

Thanks to introduce and modified it!

Regards,

Masa

Hello Masa-san,

Masakazu Adachi said:

 How did you calculate this value?

I have worked with logic for many years and I just happen to know the typical LVC output drive strength without any calculations.

To get the worst case (maximum) output impedance, the value is determined from the voltage across the output MOSFET divided by the output current through the MOSFET.

For the SN74LVC16245A:

I recommend against using the marked out low-current values, as the guard banding on the limits will produce wildly inaccurate results.

In the low state, that is V_OL / I_OL, which at 3-V supply is 0.55 / 0.024 = 22.9 Ω. Remember that this is the _maximum_ value that can occur across process variations and the full operating temperature range.

A good rule of thumb for the typical value is to take half of the calculated maximum limit, which results in 11.45 Ω -- from my experience, LVC tends to have a typical resistance around 12 Ω. You don't have to be extremely precise to get a good impedance match - as long as the output and the transmission line are close, the signal should be good.

Hello Masa-san,

Masakazu Adachi said:

1. Is it possible to do IBIS simulations with TINA-TI? The customer is not have IBIS simulator.

No, Tina-TI is not an IBIS simulator, I recommend using their favorite search engine to find a free IBIS simulator. We use ADS for our simulations, but it is quite expensive.

Masakazu Adachi said:

2. Sorry for the rudimentary question, but why is the output impedance calculated by V_OL / I_OL instead of V_OH / I_OH?

The low-state output impedance is calculated using the voltage across the low-state driver MOSFET - ie resistance is a ratio of voltage across the resistor and current through the resistor as per the definition of resistance in Ohm's law.

V_OH is the node voltage at the output of the device relative to ground, however it is not the voltage across the output high-state driver MOSFET.

As shown above, the voltage across the high-state driver MOSFET (in red) is V_CC - V_OH, so the output high-state resistance would be (V_CC - V_OH) / I_OH.

I recently released a video explaining standard CMOS outputs here: Understanding the operation of standard CMOS outputs

And we have a few frequently asked questions posted on E2E regarding logic outputs here: [FAQ] [H] Output Parameters

Hello Emrys-san,

Thank you very much for explaining in detail.

Regard,

Masa