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SN74LVC1G11: Cascading AND Gates - Powering AND Gates with the output of another AND gate

Part Number: SN74LVC1G11
Other Parts Discussed in Thread: SN74AHC1G09, SN74HCS09

My circuit is part of a safety system. When ESTOP_1_IN and ESTOP_2_IN are both high, ESTOP_OUT should be high as well, basic AND-gate functionality.

In order to reduce risks of unsafe failure of this system (ie. shorted input/output to 3V3 inside the package/die or an output driver stuck at HIGH), I have decided to add 2 more AND gates. This way, at least 2 AND gates need to fail in an unsafe manner in order to get an unsafe state at ESTOP_OUT. To achieve this, I'm powering the 2nd and 3rd AND-gates with the output of the 1st and 2nd AND-gate. 

My question is:

Are there any risks in this design that I'm overlooking?


The risks I have thought of so far:

Risk 1: Voltage drop at output

The SN74LVC1G11's datasheet shows the voltage drop between VCC and OUT at different voltages and loads. The risk here is that cascading the AND-gates will results in a too low voltage on ESTOP_OUT after the 3rd AND-gate. I do not expect there to be a problem here, the datasheet shows a drop of 0.7V at VCC=3V with a 24mA load. The load will be way lower in my case, as I'm only powering the other AND-gates (several uA) and pulling down with a 10kOhm resistor.   

Risk 2: Failure of pulldown resistors

When one of the pulldowns fails, it might leave the AND-gate input stuck at GND or floating. A short to GND would be considered "safe" in my application. However, a floating state would be unsafe as the AND-gate's behavior could be unstable. For this, I have chosen to use MELF resistors for their higher stability, moisture resistance, and operating temperature.

A production error such as tombstoning could still lead to a floating input, but I'm sure our production house can cover this with QC.

  • Hi Michael,

    Are there any risks in this design that I'm overlooking?

    Yes -- you've introduced a much higher probability of failure by overdriving the output of your gates, and having 3 gates triples the chance of failure in general. Something I don't see in your circuit is the required bypass capacitance (0.1uF) on each power supply pin, which will definitely overload the logic gates' outputs.

    Logic gates are incredibly simple and reliable devices if you use them correctly. Your circuit should definitely be much simpler than what you're showing.

    If you start stacking these in abnormal arrangements, I can't give you any guarantees of reliability.

    This would be the simplest solution, and what I would recommend using:

    If you want to add some extra protection, Zener diodes / ESD system-level protection can be used to clamp supply, output, and input signals and prevent damage to the logic gate -- which is by far the most common reason for failure of a logic device.

    If you want to have a solution that is redundant, then I would recommend something more like this:

    This would ensure that any failing device will not be able to override the output signal - ie if just 1 gate is holding the output low, then ESTOP_OUT will be low.

    Reversing the diodes / using a pull-down resistor instead of a pull-up would let you have the opposite fail-safe state - ie if just 1 gate is holding the output high, then ESTOP_OUT will be high.

  • The SN74AHC1G09 or SN74HCS09(-Q1) have open-drain outputs and do not need diodes.

  • I agree - an open-drain gate would be a good solution, if you're willing to take the risk that the gate could have an internal short to VCC. In any device there is a risk, and TI will not guarantee a failure mode for logic.

  • Thanks for your reply .

    Your redundant design is a lot simpler and more predictable!

  • Great suggestion! I prefer to keep the component count as low as possible, this helps!

  • I changed the design according to your suggestions.

    - Added ESD and Zener Clamping at 6.2V on both inputs and the output.

    - Swapped the resistor for MELF types to reduce the chance of failure.

    - Added a 0.1uF ceramic X7R capacitor close to the AND-gates.

    - Changed to three open-drain output AND-gates.

  • Hey Michael,

    Looks good to me. I realized after I posted that I copy/pasted the input pull-down resistors when I didn't need to. Considering that normal CMOS logic gates have a failure rate in the 1:billions range, I would expect a single gate to have similar reliability to this setup (ie failure is extremely unlikely). 

    I would expect an OD part to be much less likely to have a short to VCC on the output, but it's not impossible (the die is quite small, so a thermal failure could short pretty much anything -- also, VCC / GND are connected to every pin through ESD structures) and again TI won't make any guarantees on that.  That's the main reason I went with the diode solution over the open-drain solution -- even if one component failed (diode or gate), you maintain functionality - or at least fail in the low state.

  • Thanks once again. I just added the diodes back, better be safe than sorry.

    I've chosen Schottky diodes to reduce the voltage drop over a typical 0.7V diode down to 0.4V. The circuit I'm outputting towards has a Vin_low of around 1V, which is a bit too close for comfort.