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SN74LVC2G74: Output status question

Randy Chen
Intellectual 1970 points
Part Number: SN74LVC2G74

Hi,

A few questions below might need your help to clarify,

1. What is the Q and Q’ status when both PRE’ and CLR’=H? (CLK:X, D:X)

2. From datasheet mentioned note (1), what does it meant of “it does not persist when PRE or CLR returns to its inactive (high) level.”? Could you please share the waveform for reference? And does it meant the output(Q and Q’) are not stable and do not recommend to use this condition? (PRE’=L; CLR’=L; CLK:X, D:X))

3. Could you please help me to clarify the function table on below picture colored by red? 

Best regards,

Randy

  • 0
    Guru 297310 points

    1. This is shown in the last three lines of table 8-1.

    2. /PRE = L and /CLR = L is an invalid combination. Both outputs will stay high as long as both inputs are low, but as soon as one input goes high, the two outputs will go back to a consistent state.

    3. During the first bit ("unknow"), the output stays at it previous value. (Directly after power up, the state is undefined, either high or low.) During the third bit, output stays high. During the fourth bit, in case 1, the output is low; in case 2, the output Q is high.

  • 0 in reply to Clemens Ladisch
    TI__Intellectual 1970 points

    Hi Clemens,

    Thanks for the help, two more questions,

    1. wonder what does it meant of the ‘consistent state’? as below right?

     

    2. If the CLR’ goes low than to HIGH(like a pulse, below waveform for reference), what is the output(Q) behaviour? Same as waveform Q?(yellow, change from H to L), it’s as the case 1 we mention(third bit to fourth bit)? Many thanks.

     

    Best regards,

    Randy

  • 0 in reply to Randy Chen
    Guru 297310 points

    1. /PRE = L and /CLR = L is an invalid input. In this case, both outputs are high, which is inconsistent.

    2. Yes, the low pulse in the waveform is the same as as the low pulse in case 1.