This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

SN74AUP1G80: Fmax anomaly

Part Number: SN74AUP1G80

I observe some anomalies in the datasheets of AUP1G80, AUP1G79, AUP2G80, AUP2G79, AUC1G79, AUC2G79.

Let's look at 1G80:

a. There is a fclock in chap. 6.7 and there are fmax values in chap. 6.8-11. It is unclear what their relationship is.

b. It is somewhat surprising that fmax at higher supply voltages does not increase as the capacitive load is reduced.

c. In many cases the typical fmax value at 25°C is lower than the min. fmax over the temperature range.

This cannot be, no way!

One would expect the typical value to be at least twice the worst case value, the small magin, where it is, IMHO is technically implausible.

The same applies to the AUP2G80 and AUP2G79 datasheets.

d. In the AUP1G79 datasheet in chap. 6.6 and 6.8 the frequency is given in ns, should be MHz, of course.

Same for the AUC1G79 datasheet. Same for the 30pF values in AUC2G79. Same for the 30pF values in AUC1G80 and AUC2G80. Same for the 30pF values in AUC1G74. 

(Nine buggy datasheets makes a sixpack of beer for me, right?)

I am particularly looking for a (ripple) frequency divider with AUP2G80 or AUC2G80 i.e. cload <5pF.

I guess the chip is much better than the datasheet says (... compare competitor!)

  • Hi Alfred,

    You certainly did find an interesting collection of errors. I agree that the typical value should always be larger than the f_max (min) spec and that frequency should be measured in MHz and not ns.

    The f_max spec has long been one of the more confusing specs -- for example, if we list f_max in the Timing requirements as 250 MHz, that means your input is up to 250 MHz. For a D-type flip-flop, the output would be 125 MHz in this case, so I would expect F_max in the switching characteristics to be 125 MHz with a test condition of a 250 MHz input signal. Unfortunately, that is not how most datasheets are written -- they list the input frequency in both tables.

    I will add these to our backlog of datasheet fixes.

    -

    For now, were you able to find what you needed?  The AUC family is extremely fast and is optimized for 1.8V operation, while the AUP family is targeted at low power operation at 3.3V.

  • Concerning my point a.: It seems that fclock is the min fmax for a load of 30pF over the temperature range.

    It's just not clear why to specify it twice. And it is not clear why it would not increase if Cl is less.

    So, no, what I'd like to know is if in the 1G80 case there is really a hard limit of 260MHz and why.

    Sure it is not trivial to drive a clock at that frequency, but this problem is outside the scope of the datasheet.

    I am thinking about driving a (cheap!) divider from a ring oscillator output to possibly create a PLL.

    This is part of a capacitive data transmission and I want to get f as high as possible to minimize the coupling cap (put it into PCB) and its associated common-mode effects.

    Nominally I must not go above the specification of the datasheet and I suspect that it is more conservative than necessary.

    I do like AUC, please never ever think of discontinuing the AUCU04, whatever the sales prospects are...!

    (I need triple unbuffered inverters evidently and they are not in AUC or AUP, regrettably).

    I have a hard time believing that the AUC1G80 cannot do more than 275MHz under ideal conditions.

    Is there maybe a thermal limit? Or a signal integrity risk?

    Or is it that nobody assumes that anyone would have an application in that frequency range and therefore it is just not tested? 

    There are, of course, dividers/prescalers/ripple counters which can deal with such frequencies and much more, but the cost structure tends to become very different. The gap between ca. 300MHz and 1GHz is what matters.

    Isn't it time for a new fully-differential logic family maybe...?

    Or would you have a specific suggestion from another part of the portfolio that I might not be aware of?

  • Another detail: AUC74 has fmax of 350 MHz, but AUC1G74 has 275 MHz. Somehow hard to believe or to understand.

  • And concerning the datasheet of AUC74: In the logic diagram on page 2 a part is missing. 10th DS ...

  • Hey Alfred,

    Thanks for your feedback. I will note all of the issues you have brought up. If you care to review our entire datasheet portfolio, I would be very happy to put all of the errors in our tracking system so we can fix them. Unfortunately, I have not had the time to review all of them and can only focus on the ones we are updating at any point in time.

    So, no, what I'd like to know is if in the 1G80 case there is really a hard limit of 260MHz and why.

    There is no hard limit for these analog devices - they don't instantly fail when you go from 260MHz to 260.001MHz, and there is no frequency value which would provide a clear cutoff point. This is a call made by the systems engineer when the device is initially characterized, and unfortunately many of the criteria they used left with them.

    Nominally I must not go above the specification of the datasheet and I suspect that it is more conservative than necessary.

    From a practical standpoint, we (TI) will only guarantee operation within the maximum limits - typical values are not guaranteed in any way. If you want to use the devices outside the min/max limits, you of course can, but we just won't support it under warranty. TI generally puts very safe limits in our datasheets for liability reasons.

    I have a hard time believing that the AUC1G80 cannot do more than 275MHz under ideal conditions.

    I agree -- but the datasheet doesn't provide details for operation under "ideal conditions" -- we just provide the worst case limits.

    AUC74 has fmax of 350 MHz, but AUC1G74 has 275 MHz

    These two devices have different structures / die designs (although similar), so it is not hard at all for me to believe that they will have different performance, especially at such high speeds for single-ended logic. Also they were likely developed by different people at different times.

    Isn't it time for a new fully-differential logic family maybe...?

    This has been something we have considered for a long time, but we almost never get requests for differential logic. I expect when the market requires these regularly, TI will make a family to support it.

    Or would you have a specific suggestion from another part of the portfolio that I might not be aware of?

    It seems that you have scrubbed our portfolio quite thoroughly. You're really operating beyond the intended range for our logic portfolio. The majority of the portfolio I support (standard logic) isn't high speed -- anything that is high speed would be supported by a different team. 

    TI does have other teams that have high speed intended parts -- for example, our clocking team supports parts up to around 3.5 GHz:

    https://www.ti.com/clocks-timing/buffers/products.html#sort=1099max;desc& 

  • Tnx. 

    Unfortunately I do not have the time either to review all datasheets, particularly from TI, but when I am confused by an issue I look a little bit around and look more closely; experience is that similar topics are nearby and this is kind of my service, especially when there are evident copy-paste mistakes.

    With ideal conditions I only referred to the 5pF load which would apply for a ripple counter divider.

    BTW: I just found a few other great AUC devices that I had not been aware of. Solved one of my problems.

  • We definitely appreciate any feedback like this from our customers and community members. Please know that we do take the issues in our datasheets seriously, even if we can't immediately fix them. I passed along this thread to my systems team so they can take note of your comments when developing new and updated versions of our datasheets moving forward.

    Please come back any time.