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SN74HCS21-Q1: Glitch in the output of the SN74HCS21-Q1 when power up

Part Number: SN74HCS21-Q1
Other Parts Discussed in Thread: SN74LVC1G125-Q1, SN74LVC1G126-Q1, SN74LVC1G99-Q1, SN74HCS21

Hi Expert, 

I'm verifying the "AND" logic IC SN74HCS21-Q1 for our project. I found an abnormal phenomenon from this chipset. Showing the waveform below.

In it, the DSP_RST is from the output of the IC. UG1V_PG and MCU_PA15 is the input of the IC. UG3V3 is the VCC of the IC.

We can see that the output will have a glitch when VCC is rising up, even though the one of the input is low. In the time. We expect the output should be low without glitch. 

Do you know this issue? And how can we avoid this glitch appearing?  Or any other IC with the same function to recommend to us?

Thank you, 

Best regards,

Haiming.Qu

  • Below the minimum supply voltage of 2 V, correct operation is not guaranteed.

    Only devices with an OE or /OE input have guaranteed behaviour during power-up/-down, and only when the outputs are disabled. So use the SN74LVC1G125-Q1/SN74LVC1G126-Q1/SN74LVC1G99-Q1, and add a pull-down resistor at the output to generate the desired power-up state. The /OE signal can come from a microcontroller or from a reset supervisor.

  • Hi Expert, 

    The chipsets you have supplied are buffer IC. I think you are advising to add SN74LVC1G125-Q1/SN74LVC1G126-Q1/SN74LVC1G99-Q1 after the output of the SN74HCS21-Q1. If so, will the buffer IC have the glitch when the VCC is not ready? do we just need to keep the OE disable when VCC is not ready? 

    If so, I'll plan to have a try on it.

    Thank you for your feedback.

  • Yes, the buffers would go after the '21. But the '99 can be configured as a two-input AND gate.

    When /OE is high (or OE low), the output is guaranteed to be disabled, even during power up.

  • Hi Expert, 

    Thanks for your reply. If there isn't any more other IC to replace the SN74HCS21. I think I have gotten the answer from you.

    Thanks a lot.