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SN74HCS595-Q1: hot plug

Ryan Wang
Expert 6440 points
Part Number: SN74HCS595-Q1
Other Parts Discussed in Thread: SN74LV595A-Q1,

Dear expert,

Customer wants to connect pin SER, Qa~Qh to a connector to connect signal outside of the board. This connector need hot plug. Can our silicon support this?

 Or we need some external protection circuit for this hot plug?

Thanks

  • 0
    Guru 281530 points

    The Logic in Live-Insertion Applications With a Focus on GTLP application report defines four levels of isolation. HCS devices are at level 0; the SN74LV595A-Q1 would be at level 1.

    What are the devices on both sides of the connector, how exactly are they connected, and what combinations of powered/unpowered are possible?

  • 0 in reply to Clemens Ladisch
    TI__Expert 6440 points

    Clemens，

    Clemens Ladisch said:
    What are the devices on both sides of the connector, how exactly are they connected, and what combinations of powered/unpowered are possible?

    GPIO from MCU is on the other side of daughter board. 

    SN74HCS595-Q1 is on motherboard. 

    I have some questions for Level 1: 

    “by limiting the current transfer between an energized bus and the device input and output when powered down (when the power supply,
    VCC, is forced to 0 V).”

    Does "Powered down" mean unplug SN74HCS595-Q1 daughter board from motherboard which result in power lose?

    "the host system must suspend signaling during daughter-card insertion or removal."

    Does "suspend" mean put in high impedance status?

    "output-enable pin should be utilized in standard logic devices other than GTLP and FB devices"

    Does it mean /OE pin should be disabled?  SN74LV595-Q1 is GTLP device?

    Thanks

  • 0 in reply to Ryan Wang
    Guru 281530 points

    The Qx pins are outputs, but the SER pin is an input. This does not appear to make sense; why would the daughter board MCU control the shift register to set its own GPIOs? Do you mean the SER input, or the cascading QH' output?

    When hot-plugging, the devices on the daughter board are initially unpowered; the isolation levels mainly apply to those. I guess the MCU does not have overvoltage-tolerant pins? (If the '595 outputs a high signal at a voltage higher than the MCU's current VCC, then this is likely to violate the MCU's absolute maximum ratings.)

    The SN74LV595A-Q1 supporting level 1 would matter only if it were on the daughter board; in this application, you can just as well use the HCS.

    The application reports mainly talks about a large bus, where the device on the daughter board should not affect the communication between other, already-powered devices on the main board and other boards. When there is only a point-to-point connection between the shift register and the MCU, this does not apply.

    Devices on the daughter board that do not support level 2 must be disabled with /OE to ensure that they do not output wrong values during power up. The application report mentions GTLP and FB because those support level 2. (I suspect your MCU's GPIOs are configured as inputs during power up, i.e., this would not be a problem.)

    Does the connector ensure that certain pins (e.g., GND, VCC) are connected before other pins?

  • 0 in reply to Clemens Ladisch
    TI__Expert 6440 points

    Clemens,

    Great thanks for your detailed explanation.  I understand now.