The background is as following:
Use SN74LV595APWR chips in groups of three and use them in cascade, as shown below.
According to the Timing requirements of the chip manual, SER is sampled on the rising edge, but starting from the second chip, the QH' of the previous SN74LV595APWR is the SER of the next chip. This timing is different.
The measured waveform is consistent with the Timing Diagram of the chip manual. I would like to ask, is there any risk in this situation?
If it is normal, starting from the second chip, can the SER setup and hold time be adjusted according to the falling edge of the clock? Also press the rising edge card value fails. The attachment is the measured waveform.
Related waveform from CPLD to the first 595:
Related waveform from the first 595 to the second 595:
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