I have a question about Daisy chaining 2 SN74LV 595 parts together. We did this and do not have any delay in between the 2 parts. It looks like the output will change on the pos edge of SRCLK, QH’. Inside the chip, do you have inherent delays? Because there are setup and hold requirements. What do we need to do to daisy chin 2 together? The clk to data delay on the output is 1 ns min. The hold time is required to be 1.5 nsec. Can just daisy chaining them together cause a race condition? How does it not?
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