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SN74HC74: D Flip-flop output as LVDS clock signal

Arun Patil
Prodigy 60 points
Part Number: SN74HC74
Other Parts Discussed in Thread: DSLVDS1047, SN74LVC541A, DS91M125

Tool/software:

We came across an instrument that has SN74HC74PWR, the two D flip-flips as divide by two counters cascaded, the first counter is driven by 4 MHz Pierce-Gate oscillator and second counter output Q and Q bar has 3 series resistors across them. The equal resistors (R1=R2) connecting to Q outputs are of 140 ohms each and the middle resistor (Rd) is 47 ohms value. The chip is supplied with Vcc of +5V. The differential output (LVDS) signal across resistor Rd of 47 ohms is 1 MHz with peak to peak amplitude of 0.718 V (718 millivolts) that goes to 4 different sockets (CN1, CN2, CN3, CN4) in parallel. The common mode DC offeset is +2.5V (Vcc/2) The copper trace across resistor Rd to all four sockets is closely coupled differential trace of100 ohms differential mode impedance. Let us consider a case when there is no LVDS receiver connected to any of the four sockets (CN1, CN2, CN3, CN4), the current through series resistors would be Vcc/(R1 + Rd + R2) i.e. 5V/327ohms = 0.0152 Amps (15.29 mA). If all four sockets have independent LVDS receiver (EIA/TIA-644 compliant) with 120 ohms input termination resistor connected, each with 2.5 meter long twisted pair cable (differential Zo = 100 ohms), the connection being parallel on all four sockets, the effective LVDS load resistance Rde (Re 47 ohms || to four 120 ohms in parallel)  becomes Rde =18.3 ohms and current through output Q terminals will swing +/- 16.76 mA [Vcc 5V / (R1 + Rde + R2) 298.3 ohms] with reduced differential peak to voltage of 0.326V (326 mV) across Rde (on socket terminals as well as across 120 ohm termination resistor on all fours LVDS line receivers) . The IOL (max) and IOH (max) specified for SN74HC74PWR is +5.2 and -5.2 mA. Our question is whether this design is stable? What sort of performance issues to expect? We are intrigued because the Rd of 47 ohms does not match with 100 ohm differential trace impedance of LVDS signal lines and secondly, we have never seen LVDS receivers with long stubs (of 2.5 meter twisted cable for each LVDS receiver) connected in parallel to LVDS driver ouput. The PCB differential LVDS signal copper trace length from resistor Rd to parallel sockets' bank is approximately 6 cms. The common mode DC voltage +2.5V also violates the requirement [VCM = +2.4V - VID/2, VID being VOD across Rd]  specified for LVDS receiver input in compliance with EIA/TIA-644 though the LVDS signal VOD across Rd (no receiver connected, 718 mV) and Rde (fours receivers connected, 316 mV) remains within specified limits |VID| = +0.1V to +1.0V. This application is for 1 MHz clock distribution from the main device (host with 74HC74 AS LVDS driver) to four different sensor modules. The LVDS receiver differential input threshold VTH is 100 mV and hence it appears that differential noise margin (DNM = VOD - VTH) is not an issue whether single module (point-to-point LVDS signaling topology) or more than one module is connected (parallel star topology).    

  • 0
    Guru 296120 points

    In theory, an LVDS driver should inject a constant current of ±3.5 mA, which result in a voltage drop of ±350 mV over the single termination resistor. Receivers must be able to accept a voltage that is as low as ±100 mV.

    It would be possible to use a different circuit in the driver, as long as the output signal is compatible with LVDS, or as long as the receivers are capable of handling the signal. (A common-mode voltage of 2.5 V might or might not work with a specific receiver. A more modern board with a 3.3 V supply would not have this problem.)

    HC outputs have a typical output impedance of about 25 Ω (see figure 31 of Input and Output Characteristics of Digital Integrated Circuits at 5-V Supply Voltage), i.e., the effect is as if R1 and R2 were about 165 Ω. An output current of 16 mA is OK, but the actual output voltages are no longer guaranteed.

    A star architecture with a single driver for multiple lines is possible, as long as the driver is strong enough for all the termination resistors. You would get problems only with unterminated stubs.

  • 0 in reply to Clemens Ladisch
    Prodigy 60 points

    Hello Clemens,

    Thank you very much for the prompt response. We are considering to change the supply voltage Vcc from +5V to +2.5V so that the common mode DC offset voltage is +1.25V which will help if there is +/-1 V ground shift between the host (driver side) and the connected modules (receiver side). We would also like to have the differential voltage VOD of 0.6 V across the resistor Rde when all four modules (with 120 ohm input terminated receivers) are connected to the host. From your reply, taking into account that 74HC74 output impedance of 25 Ω and maximum sourcing current of 40 mA, we arrived at two sets of resistors as follows. 

    1. R1 = R2 = 4 Ω (closet value 4.02 ohms 0.1% E192 Series) and Rd = 47 Ω ; when all four modules are connected the maximum output current Io = [(2.5V) / (R1+R2+ twice the output impedance)] = 32.76 mA, VOD = 0.6 V (as effective Rd is 18.3 Ω).

    2. R1 = R2 = 13 Ω (closet value 13.02 ohms 0.1% E192 Series) and Rd = 120 Ω ; when all four modules are connected the maximum output current Io = [(2.5V) / (R1+R2+ twice the output impedance)] = 25 mA, VOD = 0.6 (as effective Rd is 24 Ω).

    Please let us know which set of resitors would you recommend. Does it really matter if Rd value is not close to the differential line impedance of the traces? 

     

  • 0 in reply to Arun Patil
    Guru 296120 points

    Rd is not needed at all. You need termination only at the receivers.

    With a 2.5 V supply, HC outputs are much weaker; 32 mA will not be possible.

    When you are changing the board anyway, why not use the DSLVDS1047, or at least the SN74LVC541A?

  • 0 in reply to Clemens Ladisch
    Prodigy 60 points

    We worked out a solution using repeater (DS91M125) but the whole process of testing, approvals to final implementation will take another 8 to 10 months at least. Meanwhile, we are trying to see if interim quick and economical fix can be done for better performance for some of the end users where application is safety/accuracy critical. Sometimes, none of the module is connected leaving the LVDS signal line open circuit as the end user process event requires the host instrument only for the data processing using CAN protocol communication with the ancilliary connected units