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SN74AUC74: Will only rising edges on CLK result in D being represented on Q if ~CLR is already HIGH?

Simon Merrett
Prodigy 110 points

Part Number: SN74AUC74

Tool/software:

I need to capture a rising edge and plan to use a fast logic part such as SN74AUC74, because I have seen elsewhere on TI forums that although parts are not specified for jitter performance, a high speed, low propagation time (Tprop) part is likely to come with low jitter.

I need to gate the rising edge and plan to use the ~CLR pin to provide the gating function. With D tied to logic HIGH, the next rising edge on CLK after ~CLR is pulled logic LOW should be represented on Q after Tprop. If ~CLR is pulled logic HIGH while CLK is already logic HIGH, what state Q will be in Tprop later? Assume ~PRE is logic HIGH throughout.

To give another way of looking at my question, I have extended the function table in blue font and would be grateful for completion by TI community:

If ? = Q0 and ?? = Q0, this is what I need. If not, are there any parts which are high speed / low Tprop, allow gating and will ONLY change the output on a rising edge of one input, such as CLK?

  • 0
    TI__Genius 15501 points

    Hi Simon,

    While CLR is low the device will output LOW. Then as CLR goes high Q0 will be LOW until the next rising edge of the clock. If D is tied to HIGH the device will then output HIGH on the CLK transition. If D is tied to LOW then on that clock transition the device outputs LOW.

    In Both of your blue lines here CLK is not transitioning and CLR is going from LOW -> HIGH therefore the outputs in those states would be transitioning to LOW.

    If I understand what you are asking for correctly I believe what you want is to tie D to HIGH go through one rising edge of CLK minimum then hold in high state. This will have !Q be LOW for standard operation. Then when CLR goes high it will change !Q0 to HIGH for you to perform your operation. The device can then be "reset" for the next edge by having another rising edge on the CLK.

    The other option which seems more intuitive to me would be to hold CLR high in standard operation and tie your edge to be detected to CLK. D is always HIGH, so the device will output HIGH on your edge detect. then reset the device with a pulse LOW to the CLR pin.

    Regards,

    Owen

  • 0 in reply to Owen Westfall
    Prodigy 110 points

    Thank you very much Owen. I don't think it answered my question so I will try and use a timing diagram like you did to set out my area of uncertainty better. In the diagram below, what would Q be in the unknown state period if CLR goes high when CLK is already high?

  • +1 in reply to Simon Merrett
    TI__Genius 15501 points

    The Unknown time here will remain LOW.

    Regards,

    Owen