Part Number: SN74V263
Tool/software:
Hi,
I'm working on a project using the SN74V263 FIFO in standard mode with a 9-bit input and output bus width. I'm facing an issue with my write and read operation and the status flags.
My system uses an external 50 MHz oscillator to drive the WCLK pin, which writes data into the FIFO. My microcontroller (MCU) is a PIC running at 120 MHz (1 machine cycle = 60MHz).
The Problem:
1. During Write:
I have configured a change notification interrupts for HF and FF flags. I am setting WREN = 1 when HF = 0 but FF flag is also changing to LOW indicating that write didn't stop.
I am using the following code structure for my write operation:
void enable_fifo_write(void)
{
// Disable reading from FIFO
FIFO_REN = 1;
// Enable writing into FIFO
FIFO_WREN = 0;
// Perform Partial Reset
FIFO_PRS = 0;
fifo_usec_delay(1);
FIFO_PRS = 1;
// Clear interrupt flag
// Enable change notification interrupt for FF, EF and HF flags
// Enable CN interrupt globally
// After the first write is performed,
// EF goes high after two low-to-high transitions on RCLK
FIFO_RCLK = 1;
FIFO_RCLK = 0;
FIFO_RCLK = 1;
FIFO_RCLK = 0;
}
2. During Read:
I am trying to perform a read operation when the FIFO is full (FF = 0), but the flag status isn't changing especially the FF flag.
As per my understanding when FIFO is FULL (FF = 0), a single read operation will cause FF to change from LOW to HIGH after 2 RCLK transitions.
I even tried reading the FIFO up to the max FIFO size but didn't observe any change in the flags (FF, HF and EF).
I am using the following code structure for my read operation:
void read_data_from_fifo(void)
{
uint16_t readcount = 8200;
while(readcount-- > 0)
{
fifo_read_init();
raw_data = fifo_read_start();
}
}
void fifo_read_init(void)
{
FIFO_REN = 0;
__asm__ volatile("nop");
FIFO_OE = 1;
__asm__ volatile("nop");
FIFO_RCLK = 0;
__asm__ volatile("nop");
// REN should be LOW when the RCLK goes from LOW->HIGH.
FIFO_RCLK = 1;
__asm__ volatile("nop");
}
void fifo_read_start(void)
{
uint16_t read_data;
// When RCLK is HIGH, OE should go from HIGH-> LOW before reading from the port.
FIFO_OE = 0;
// REN should go high while RCLK is HIGH
FIFO_REN = 1;
__asm__ volatile("nop");
FIFO_RCLK = 0;
__asm__ volatile("nop");
// By this time tOLZ time has elapsed and data on Q0-Qn are valid.
// Read 9-bit data from the FIFO's output port
read_data = PORTD & 0x01FF;
return read_data;
}
My Analysis
- I have correctly configured the device for standard mode during the master reset.
- I'm concerned that my MCU, despite running at 120 MHz (1 machine cycle = 60MHz), is too slow to keep up with the 50 MHz write clock, and the FIFO is becoming full before my software can react.
- I believe my read function may not be adhering to the timing requirements of the SN74V263.
Can you please advise on the correct sequence of signals for a single-word or continuous read in standard mode, paying close attention to the timing requirements for REN, OE, and RCLK?
Thank you for your assistance.
Regards,
Tanuj Kumar
