Part Number: CD4043B
Hello TI,
I was simulating the CD4043B (S/R latch) using TINA and I found an issue.
When S=0 and R=0 the output (Q) seems to be toggling between logic '1' and logic '0' whenever the enable pin is toggling.
So when enable is high, the output will also be high even when S=0 and R=0.
I used the pspice model given in this forum.
https://e2e.ti.com/support/logic-group/logic/f/logic-forum/887626/cd4043b-pspice-model?tisearch=e2e-sitesearch&keymatch=CD4043B#
Is this happening because of some error in the pspice model or something else?
Thanks.
