What level/state is expected on pin B if VCC is 1.8V, OE = 0 and pin A is 5.0V?
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Thank you for your reply.
I do not expect SN74CB3T1G125 to function correctly in such conditions. SN74CB3T1G125 pin B is connected to 1.8V tolerant FPGA pin so i have to decide whether to remove SN74CB3T1G125 or not from the board in order not to damage the FPGA.
Although, i think that FET does not open with VCC=1.8V so pin B will be in Z condition, i do not have enough knowledge in this area so decided to ask TI E2E Community. May be someone has faced this situation.