CDCLVC1104 and SN74AUP1G79 latch up?

Jordan Fine

Hi,

I have a lvcmos clock buffer driving an D-Flip flop, and lvcmos buffer listed above. Once the boards came back assembled the clock line signal was attenuated and offset. At first I thought the oscillator was bad, but after pulling off the oscillator from the board, I measured a DC value of 3.3 V on the clock line. Either the flip flop or the buffer is bad. This happened on multiple boards. Is this a latch-up issue? I have used this design in the past with a slightly different layout. Any ideas?

FYI. The clock line is not pulled down or ac coupled to the oscillator. From my reading I should not have to with LVCMOS logic.

Thanks

Jordan

over 10 years ago

0 C. Ryan Land over 10 years ago

TI__Genius 9860 points

Hi Jordan,

Can you provide a schematic along with scope shots of the waveform of the attenuated/offset clock signal?

-Ryan

0 Jordan Fine over 10 years ago in reply to C. Ryan Land

Prodigy 40 points

I have attached the scope output for the clock line. Notice that it is offset and attenuated - should be 3.3 Vpp, 0V low.

0 Jordan Fine over 10 years ago in reply to Jordan Fine

Prodigy 40 points

This is the buffer configuration

0 C. Ryan Land over 10 years ago in reply to Jordan Fine

TI__Genius 9860 points

Hi Jordan,

I have two more questions.

1. Is the measured clock line going into the input of the flip flop or is it the Q output of the flip flop? (I assume it is the clock input unless you are also using the clock to input data for testing).

2. Does the problem disappear if you remove the flip flop from the board?

0 Jordan Fine over 9 years ago in reply to C. Ryan Land

Prodigy 40 points

Hi Ryan,

The clk is going into the clk input of the flip flop.

I removed the buffer and replaced the flip-flop with a new one and everything works. Before not only was my buffer stuck at high, but my FPGA was acting strange, i.e. the counter I had was outputting the wrong frequency. Likely a result of the bad clock.

If worse comes to work I will just leave out the buffer. I am surprised at this behavior. I ran this circuit before without issue. My clock can handle 40 mA drain current and I have since added a 51K pulldown to avoid latch-up.

I am debating on whether to add a new buffer to the working circuit to see if the problem still exists. Probably will try on one board.

Thanks for the help.

Jordan

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CDCLVC1104 and SN74AUP1G79 latch up?