Hi,
I am interested in the timing mismatch from one channel to the next. My application is a unidirectional voltage translation from 3V3 to 1V8, with 3V3 on Dn side and 1V8 on Sn side.
I have 4 critical signals that need to match very well. A fixed delay is ok, but the delays should be matching between these four signals
Thanks,
Alvaro