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D Flipflop , SN74AHC74QPWRQ1 clock rise time

Other Parts Discussed in Thread: SN74AHC74, LPV521


I am driving the clock input of SN74AHC74QPWRQ1 from the output of a comparator based on LPV521MGE.

The LPV521 has a slew rate of 2.5V/ms as its a very low power opamp. The datasheet of the SN74AHC74 FlipFlop says  "Input transition rise or fall rate" shall be maximum of 100nS/V ( VCC = 3.3V). So I am out of spec.

But in the first page of the FlipFlop datasheet, in the description area, it is said " Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs".

So.. is it safe to directly connect the LPV521 out to clock input of Flipflop or do I need to use a Schmitt trigger buffer?

  • Hi Sonu,

    With an input that slow, you really need a real Schmitt-trigger (ST) input buffer.  Slow inputs can cause excessive current, oscillation, and even damage the device.

    Watch out for some flip-flops that claim to have 'ST Action' -- this doesn't mean that they have ST inputs, just that they are slightly more tolerant to slow inputs (~200 ns/V instead of ~20ns/V).  You can tell if they have real ST inputs when V+ and V- are specced, and there's no input transition rise/fall rate limit listed.

    Here's a great app note that goes into detail about ST's and why you might need one.

  • Thanks Emrys! I understand it now .