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SN74AUP1G80 Output Rise Time

Ryan Andrews
Guru 62786 points
Other Parts Discussed in Thread: SN74AUP1G80

Hello,

I'm using the SN74AUP1G80 as a clock divider and was wondering how to determine the expected output rise/fall times. My CLK input is a 16MHz LVCMOS clock signal operating at either 1.8V or 3.3V. Right now I'm measuring ~10ns rise times on my /Q output (8MHz).

I see that the Switching Characteristics tables specify max frequency (fMAX) and propagation delay (tPD). As the load capacitance increases, fMAX decreases, more so at the lower supply voltages. How is fMAX determined? Are there other devices in this family that may give me a sharper clock edge?

Thanks and regards,

  • 0
    TI__Guru 58390 points
    Hi Ryan ,

    the output rise and fall time will depend on the load. the RC load at the output which mainly includes the trace parasitic of the board .
    The higher the load , the higher the rise /fall time.
    Having an IBIS model to simulate the prop delays might be a good idea to estimate .
    Could you consider AUC1G family which is one of the fastest in terms of prop delay and the frequency rate.