In Logic Guide by TI,attached,5V TTL and 3.3V LVTTL trigger voltage is 1.5V.Can you explain why?And WHY CMOS trigger voltage is 1/2 VCC?
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The switching threshold is designed so that you get the largest possible noise margin.
For (LV)TTL, VOL = 0.4 V and VOH = 2.4 V, so the threshold is in the middle of this interval (1.4 V) so that you get 1 V noise margin in both directions. (The actual threshold depends on VCC and might have hysteresis, so it's near both 1.4 V and 1.5 V; see below.)
For CMOS, VOL and VOH are symmetrical, so the middle of the VOL/VOH interval always is half of VCC.