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SN74LVC1G86-Q1: Race Conditions Used for Testing

Richard Jiang88
Prodigy 10 points
Part Number: SN74LVC1G86-Q1

I've looked through the datasheet for this product and didn't see anything about how close transitions in the two inputs to the XoR could get, with respect to time, in order to avoid a race condition. Is there a popular search word for what I'm looking for?

I am interested in doing timing measurements where a square wave is sent along two different paths. The ends of each path will be connected to the XoR. I am hoping to see some pulses at the output of the XoR due to timing skew. If I knew that threshold value for the XoR I could qualitatively say whether or not the timing skew of my signal between the paths is greater than or less than that threshold value.

  • 0
    TI__Mastermind 24485 points
    Hello Richard,

    There is no specification for a "race condition" per se, but what i understand you are looking for is that the output is going to put out a pulse width that is equivalent to the skew between the two inputs to the XOR gate.

    In this case it will be heavily dependent upon on the rise and fall time on the output. We don't spec rise and fall time because it is heavily dependent upon the loading conditions (both resistance and capacitance).
    The output of the device will react a few nanoseconds later based on the tpd in the datasheet, but both inputs will have the same tpd.
    If for example, the inputs are different by 1microsecond, then the output will definitely create a solid pulse, but if you are trying to see a skew of single digit or even 10s of nanoseconds, you might have some issues. The device will try to rise during the offset, but may not reach the full VCC output, you will likely see just a small glitch at the output, especially if the capacitance is high at the output.

    Hopefully that helps to answer your question.

    Best,
    Michael