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CD4020B: Counter/Divider "fully static operation" ?

Part Number: CD4020B

4000 series of Counter/dividers ie 4020 list "Fully Static Operation"   but there is no mention of what "fully static operation" is/does or its limitations.  Does this mean the counter retains count after power down and then power up?  If so are their specs on using this function?

  • Hello David,

    This essentially means that there is no minimum clock frequency that is required for operation. Meaning it will retain its data and continue to propagate data on a clock edge no matter how much time passes between clock edges.

    As long as the device is powered, it will maintain its most recent state. The device will not maintain data through power cycles.
    I hope that this is clear, please let me know if you have additional questions and I would be happy to help!

  • Thanks for the answer.  But it begs a rather odd question in that by specifying this, doesn't it imply that other logic devices with latches / flip-flops which do not specify "fully static operation" loose track of their state over time?  Or am I missing something?

  • All CMOS devices have fully static operation. But when Harris first introduced this device, it was a feature worth mentioning.

  • David,

    I agree with you on this point.
    I am not aware of any devices within our listing of counters/flip flops that do not work in fully static operation.
    Even when I look at older devices, they will have Clock frequency minimums that are 0 MHz, implying "fully static operation" as per the way this is defined.
    I understand exactly what you are saying, but I suspect this is some legacy terminology that was meant to reinforce the idea, but isn't necessarily useful.

  • Thanks all, fully understand and makes sense. Thanks.