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CD74HC85: What is typical (and max) prop delay time at Vcc=3.3V CL=15pF?

Part Number: CD74HC85

The datasheet only lists prop delay times for Vcc = 2V, 4.5V, 5V, 6V.  Prop delay degrades significantly at 2V.  Can you provide typical (and max if also available) prop delay at Vcc=3.3V?  CL=15pF.  Mainly interested in A=B case, which seems to be a few ns faster at 5V.  Thank you.

  • Hello Tanaka-san,
    This is something we can test in the lab for a typical device, however the characterization was done at the values shown on the datasheet and I don't have data available at interim values. It will be at least one week before I can get the bench test data due to availability of equipment in our lab (there is some construction going on). Please let me know if you would like me to move forward with getting parts and doing this test.

    You can use linear interpolation to get a reasonable estimate of the 3.3V delay at 50pF, however we don't have data for 15pF. This device was specified/optimized for 5V operation (more than 20 years ago, by Harris Semiconductor), so the characterization was not done at modern standard voltages.
  • Hi Emrys,

    Thank you for your response!  Yes, if you can measure the typical prop delay for 3.3V, that would be very helpful. I am mainly interested in the "match" case, but if the inequality is easier to measure, then I can estimate that the match will be a tad faster than the inequality.

    I don't think the prop delay can be linearly interpolated, because the 3 data points are very non-linear: 30ns@6V and 35ns@4.5V, but 175ns@2V.  With this level of non-linearity, 3 points are insufficient to estimate the non-linearity.

    I was thinking of using XOR into OR (XNOR into NAND is significantly slower).  However, if the HC85 is fast enough, it provides a nice 1-chip solution which is more desirable.

    Thank you again for your help.  Happy New Year!


  • Hello Tanaka-san,

    I have tested this device on our bench with approximately 15pF load (8pF probe + breadboard parasitics + input capacitance) and have results to share with you.

    The average delay I saw was 30.53ns, with a maximum of 32.0ns -- with a single input switching.

    When I switched all inputs except for one, I saw an increase of ~2.2ns with a maximum of 34.2ns.

    I also completed the linear interpolation of the datasheet values to show what TI will guarantee on the device.

    Note that the bench data at 3.3V, 25C is only a typical value taken on a small subset of devices and is not guaranteed by TI.  The blue line is the maximum value guaranteed by the datasheet at 25C, and the other lines represent the guaranteed maximum value across temperature.

    You are correct that this form of linear interpolation is not perfectly accurate - there is a smoother line that would fit this more accurately, however it is our accepted method for guaranteeing values in-between our datasheet given numbers.  This makes the estimate very safe.