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SN74LV1T34: typical and max supply current draw

Part Number: SN74LV1T34
Other Parts Discussed in Thread: SN74LV1T08

Hello,

I’m trying to determine the typical and max supply current draw that the SN74LV1T34 part needs. Page 3 of the datasheet says that worst case (per chip) continuous supply current is 50mA.

  • What is the worst case current for non-continuous?
  • And why is this listed as +/-50mA when this is a single supply part?

-          Page 5 of the datasheet shows a no-load supply current max of 10uA. It then specifies a ‘delta’ supply current max of 1.5mA (under certain circumstances but no output current).

  • Why does this supply current specification talk about ‘one input’ and ‘other inputs’ when this is a single input device?
  • What does ‘delta’ supply current mean in this context? Does it mean that you add 1.5mA for each shift condition?
  • What is the worst case supply current (for Vcc = 5V, at full high and low level output current) for any level shifting configuration?
  • Hi Michael,

    I will try to clear things up a bit, one piece at a time. You can find many answers here: Understanding and Interpreting Standard-Logic Data Sheets and in our FAQ (linked in my signature)

    I’m trying to determine the typical and max supply current draw that the SN74LV1T34 part needs.

    Under what conditions? You haven't told me what load you're driving or what your supply voltage is. Are you planning to translate a signal? What's the frequency? Input voltage/edge rate? Output load? Perhaps you can tell me a bit about your application.

    Page 3 of the datasheet says that worst case (per chip) continuous supply current is 50mA.

    No, it doesn't.  It states that the absolute maximum current through the supply or ground pin is 50 mA -- there's a difference! An absolute maximum lists the amount of current the device can withstand before being damaged.

    With this specific device, you would violate the per-pin spec of 25mA (Io Continuous output current) before you violated the 50mA supply current. For any normal system, you should get nowhere near these values. Try to stay near or below the IOH/IOL specs in teh recommended operating conditions table.

    What is the worst case current for non-continuous?

    How do you define 'non-continuous' current?  And why are you trying to drive so much power through a logic gate? I would recommend avoiding the current limits (25mA per output pin, 50mA per supply pin) regardless of how short the pulse is.

    And why is this listed as +/-50mA when this is a single supply part?

    Current can be sourced from or sunk into any push-pull output. The + and - refer to the directions of current.

    Page 5 of the datasheet shows a no-load supply current max of 10uA. It then specifies a ‘delta’ supply current max of 1.5mA (under certain circumstances but no output current).

    Why does this supply current specification talk about ‘one input’ and ‘other inputs’ when this is a single input device?

    The test conditions were likely copied from similar devices that have other inputs (for example, SN74LV1T08.  If the device doesn't have other inputs, then you can disregard the statement.

    The 10uA is a _maximum_ supply current.  CMOS devices very commonly operate closer to 1nA for static supply current.  I just measured one today at 250pA from an older logic family than the LV1T devices.

    What does ‘delta’ supply current mean in this context? Does it mean that you add 1.5mA for each shift condition?

    No, this is a specifically defined spec for supply current under the listed conditions.  You can read more about the definitions of logic datasheet specs here: Understanding and Interpreting Standard-Logic Data Sheets

    It is intended to give information about shoot-through current when an input is not driven all the way to the rail. If you search a bit on E2E (or the internet) you can find many explanations for how shoot-through current works on CMOS inputs. Since the LV1T family's inputs are designed to be operated below the rail, this issue can come up in many applications for up-translation.

    What is the worst case supply current (for Vcc = 5V, at full high and low level output current) for any level shifting configuration?

    I would recommend keeping the device within the IOH specs in the recommended operating conditions table.  In that case, you should see maximum static current of ~8mA. 

    Also, you might find this application report interesting/useful: CMOS Power Consumption and Cpd Calculation