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SN74LVC1G00: SN74LVC1G00

Part Number: SN74LVC1G00

Does this part support a full power down mode?

This part is too small to solder and test.

  • Hello Sripriya,

    What do you mean by "full power down mode" -- please define in terms of supply, inputs, and outputs.

    This device is available in 7 packages -- I have found that DCK (the most popular, 0.65mm pitch) and DBV (the largest, 0.95mm pitch) are relatively easy to solder if you want to test it out using a breakout board.  TI offers this one that I have used on occasion: www.ti.com/.../DIP-ADAPTER-EVM

  • We want output in the high impedance state during power down.

    Our inputs are held high before power down and we don't want it to be propagated to the output.

  • Hi Sripriya,
    'during power down' is still a vague statement.

    If the supply pin of the device is at 0V, then the output will be in the high impedance state as defined by the Ioff spec (table 7.5).

    If the supply pin is ramping from Vcc to 0V, then the output will remain on as long as the FETs remain biased (usually until ~1V supply), and the output will act accordingly. If you need the output to go high impedance _before_ the supply is off, then and additional device would be required -- for example, an analog switch could be used to disconnect the output/put it into a high-impedance state.
  • Thank you.
    I wanted to make sure output goes into high impedance with Vcc=0.