Hi,
My customer is interested in using this SN74AUP1G80 as a clock divider as shown in the app notes. It would be clocked at ~100Khz.
Is there a timing relationship that must be maintained between when override clock goes from driven override mode to a high-impedance mode relative to the input clock?
Thanks,
Chuchen
We are interested in using this DFF as a clock divider as shown in the app notes. It would be clocked at ~100Khz.
Is there a timing relationship that must be maintained between when override clock goes from driven override mode to a high-impedance mode relative to the input clock?
