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SN74AVCH4T245: SN74AVCH4T245 Powerdown Backflow

Cassidy
Prodigy 550 points
Part Number: SN74AVCH4T245

Hi,

I'm looking at the SN74AVCH4T245 datasheet and have a few questions:

  • Datasheet states the outputs are disabled to prevent damaging current backflow when the device is powered down.
    • Is this independent of the the Direction pins are set to? In other words, are ALL I/Os put into high impedance states regardless of whether the pins are set to inputs or outputs?
  • The Ioff spec shows that both VCCA and VCCB can be 0V and the outputs will still be disabled.
    • Why is the terminology of "Partial-Power-Down Mode" used? Why would it not be just "Power-Down Mode" if no voltage is supplied to either power rail?
  • Basically, I just need to ensure that when no voltage is supplied to the chip, if the inputs of the chip are driven, is back-power prevented in all cases as long as OE pin is tied to VCC via resistor?

Thank you!

  • 0
    TI__Mastermind 42670 points

    Hi Cassidy,

    Please see the text in red, thanks.

    • Datasheet states the outputs are disabled to prevent damaging current backflow when the device is powered down.

      • Is this independent of the the Direction pins are set to? In other words, are ALL I/Os put into high impedance states regardless of whether the pins are set to inputs or outputs? You are correct all I/O's will be put into high impedance regardless of what the Dir pin is.

    • The Ioff spec shows that both VCCA and VCCB can be 0V and the outputs will still be disabled.

      • Why is the terminology of "Partial-Power-Down Mode" used? Why would it not be just "Power-Down Mode" if no voltage is supplied to either power rail? It is used because it covers systems that are partially powered down. If VCCA is powered and VCCB is 0V then the system is partially powered down. Power-Down mode would imply the whole device isn't powered which wouldn't cover a device that is partially powered down.

    • Basically, I just need to ensure that when no voltage is supplied to the chip, if the inputs of the chip are driven, is back-power prevented in all cases as long as OE pin is tied to VCC via resistor? Yes the Ioff circuitry will take over when either one or both rails are at 0 V and a pull-up resistor on OE will ensure high impedance during power-up or power-down.