SN74ALS112A: Timing of asynchronous Flip Flops

william foley

Prodigy 20 points

Part Number: SN74ALS112A
Other Parts Discussed in Thread: SN74ALS74A

How long does it typically take to CLEAR a SN74ALS112A ?

Is it the same for the SET ?

What is the shortest acceptable interval between active clock transitions for a SN74ALS74A ?

How long does it take (after the clock edge) to synchronously store a 1 in a cleared SN74ALS74A D flip flop ?

over 5 years ago

0 Emrys Maier over 5 years ago

TI__Guru* 96681 points

Hello,
The timing specs are located in the recommended operating conditions table -- which is different from our newer devices that list it in a separate "switching conditions" table.

The PRE\ or CLR\ pin must be held low at least 4 ns to set or reset the device (the t_w "Pulse duration" spec in the recommended operating conditions table).

The minimum pulse width for "CLK low" is 5.5 ns. For "CLK high" it is 4.5 ns.

*Edit*

Sorry I missed your last question. There is no time requirement after the clock edge to hold the data line 'high' to store a 1. (hold time is 0 ns). It will take between 3 and 8 ns for the output to switch 'high' after a 1 is clock through. This is found in the 'switching characteristics' table.