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SN74HC165: QH ouput voltage abnormal

Part Number: SN74HC165


QH pin of SN74HC165PWT will jump from high level to low level (normally high level).           

When the input of SN74HC165 parallel port works normally, it is 10K resistance pull-up(CheckD1~D10).           

Is there any risk of damage to the chip by hot plugging and grounding these parallel ports during detection?           

Or there are other possible reasons for abnormal QH voltage.

By default, when all pins of CheckD1-CheckD10 are pulled up (no pins are pulled to DGND), the output of SHI_QH2 should always output high level;

while the output of abnormal machine (U2 abnormality), SHI_QH2 has low level; the following figure is the waveform captured by the FPGA terminal.



  • Hi Jerry,
    Yes, there is a risk of damage to the chip by hot plugging and grounding the parallel ports of the device. The outputs should never be set to output while also being shorted to ground - this could generate excessive current and damage the device.

    Hot-plugging applications also typically have a higher likelihood of ESD damage -- if the device is exposed to human interaction (via a port, for example), then system-level ESD protection should be added.
  • Hi Emrys,

    Are there any protective solutions recommended for these pins?
    Thank you very much.

  • The way to protect them is to not short them to ground while they are active, and to have system level ESD protection at any external connectors.

    If there is no way to prevent shorting to ground, a series resistor can be used to limit current (Ohm's Law: V=I*R)