CD74HC390 Maximum clock frequency at Vcc = 3.3 volts

Mike Bower

Other Parts Discussed in Thread: CD74HC390

I need to divide a 20.48 MHz clock by 20 to realize 1.024MHz clock for an A/D. I originally intended to use a CD74HC390; however the data sheet is a little unclear.

According to the data sheet, the f_MAX is a function of Vcc. The specifications are as follows from the datasheet (SCHS185C) are as follows:

Vcc f_MAX @25C

-------------------------------

2V 6MHz

4.5V 30MHz

6V 35MHz

What is the minimum f_MAX at Vcc = 3.3V?

Is there a better part I should be considering? CPLD's aren't an option in this design. I'd also like to keep the chip count low.

Thanks,

Mike

over 13 years ago

0 Chris Cockrill over 13 years ago

TI__Mastermind 46480 points

I dont have any hard data but in general the max frequency will start quickly dropping off around 2.5V. Above this it drops slowly. So at 3.3V my guess would be about 20-25Mhz would be the Fmax.

0 Mike Bower over 13 years ago in reply to Chris Cockrill

Prodigy 20 points

Thanks. It seems a little too close for comfort, so I intend to use Vcc=5V and use a SN74CB3T1G125DBVR to shift the level back to 3.3volts.

Logic

Logic forum

CD74HC390 Maximum clock frequency at Vcc = 3.3 volts