I need to divide a 20.48 MHz clock by 20 to realize 1.024MHz clock for an A/D. I originally intended to use a CD74HC390; however the data sheet is a little unclear.
According to the data sheet, the fMAX is a function of Vcc. The specifications are as follows from the datasheet (SCHS185C) are as follows:
Vcc fMAX @25C
-------------------------------
2V 6MHz
4.5V 30MHz
6V 35MHz
What is the minimum fMAX at Vcc = 3.3V?
Is there a better part I should be considering? CPLD's aren't an option in this design. I'd also like to keep the chip count low.
Thanks,
Mike