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CD40109B: input over-voltage protection diode circuit

Part Number: CD40109B
Other Parts Discussed in Thread: SN74LVC1G08, SN74LVC14A

This is my CD40109B circuit w/ R26.1 = 4x10K, R25.1-A = 4x100K and Cx.1-.4 = 47pF:

To protect against the Input rising above the Vcc input, I expect that the input protection diode circuit shown in the bottom part of Fig.1 below will suffice assuming the current through the R26 resistor does not exceed the max input current.

However, I have some uncertainties...

a) I assume/expect that the max input current per pin rating from the datasheet

is the rating of the input protection circuit shown at the bottom of the datasheet's Fig.1 (since the figure states "*All inputs protected by COS/MOS protection network"). However, the figure shows the top of the diodes connected to VDD, not VCC. Is this an error, or am I misunderstanding the function/purpose of this figure (or perhaps both are true :) ).

For example, if VCC is a smaller value than VDD, and these inputs are clamped to VDD, then it seems the inputs would have a limited range based on VDD (which doesn't make sense to me based on the level shifting function of the IC).

b) Again with Fig.1, the top portion of the diodes show two diodes connected anode-to-anode; I don't understand what this can protect, unless I assume that these are only protecting when the top diode reaches its reverse voltage rating. If not, how does this circuit protect? If so, what is that voltage rating that it clamps at?

c) Is there any documentation available already that explains these details? 

d) The datasheet is an old photocopy with changes (I assume TI obtained this design through the purchase of another company). Will TI create an updated datasheet anytime soon?

  • The pictures didn't show, so I must have pasted them incorrectly... I'll try again...

  • Hi James, and welcome to the forums!

    Yes - the E2E posting system is very particular about how images get put into posts. I have found the best method to be just save them somewhere on my hard drive then use the "Insert/Edit Media" button to get them into my post. Sorry for the hassle.

    ----

    You ask a lot of valid questions here. I'll separate them out here, a little out of order:

    Is there any documentation available already that explains these details? 

    Not anything that I have found. I will be happy to share everything I know here.

    The datasheet is an old photocopy with changes (I assume TI obtained this design through the purchase of another company). 


    Yes - this device was acquired from Harris Semiconductor (listed at the top left of the datasheet), and the datasheet has not been changed with the exception of pasting TI's logo & our literature tracking value on there -- and the typical addendum for orderables/mechanical information.

    Will TI create an updated datasheet anytime soon?

    Probably not any time soon. We do have plans to update the datasheet, but 'soon' is the problem. We have ~1500 datasheets remaining in our group that need to be updated to the modern TI format, and not that many resources assigned to work on them. Many of them have errors, are more modern, and/or have a large customer base that make them a priority.

    In this particular case, there's a huge amount of work to do to get this into the correct format. Since the part is very old and it's not a very popular function, it's likely that the datasheet will stay the way it is for the foreseeable future -- unless we find a glaring error that is causing problems for our customers, in which case we would have no choice but to prioritize the update.

    Again with Fig.1, the top portion of the diodes show two diodes connected anode-to-anode; I don't understand what this can protect, unless I assume that these are only protecting when the top diode reaches its reverse voltage rating. If not, how does this circuit protect? If so, what is that voltage rating that it clamps at?

    You've got it exactly right. The back-to-back ESD diode protection circuit is extremely common in devices that don't use a positive clamp diode. This circuit provides a short circuit for ESD events (over 1kV), but appear to be an open circuit for lower voltages. This configuration allows the input voltage to exceed the supply voltage without clamping the input voltage. We typically call this an "over-voltage tolerant" input.

    I see an error in the datasheet that was likely overlooked for a very long time due to the added figure for the input structure. If you look at the MAXIMUM RATINGS, Absolute-Maximum Values: on the first page, this line:

    DC INPUT CURRENT, ANY ONE INPUT .................  ±10mA

    The "±" symbol should be a "-" only -- without a positive clamp diode, there should not be a positive input current rating of 10mA (positive current is going in to the device). This device will actually only allows 1μA (max) to flow into the input. I will add this to our errata list so we don't miss it when the datasheet is updated.

    I assume/expect that the max input current per pin rating from the datasheet is the rating of the input protection circuit shown at the bottom of the datasheet's Fig.1 (since the figure states "*All inputs protected by COS/MOS protection network"). However, the figure shows the top of the diodes connected to VDD, not VCC. Is this an error, or am I misunderstanding the function/purpose of this figure (or perhaps both are true :) ).

    Hopefully the previous answer covers this for you. Please let me know if I can be of further assistance regarding this.

    To protect against the Input rising above the Vcc input, I expect that the input protection diode circuit shown in the bottom part of Fig.1 below will suffice assuming the current through the R26 resistor does not exceed the max input current.

    In your circuit, I don't see the input source, or any information regarding the input signal - so I can't really comment on anything regarding that. I also see that you have an RC filter connected directly to the inputs of the device.  I would _highly_ recommend against this, since the CD40109B is a CMOS device, and the inputs will not react well to slow input edges. There's an FAQ on this topic here:

     

    If this answers your questions, please click the green "this resolved my issue" button -- if not, just reply and I will continue to help any way I can.

  • Hello Emrys,

    Thank you for your detailed and prompt answer. It comes as a refreshing breath of air!!

    Now... to try and work my way out of the "rabbit hole"... I have two follow-up questions:

    a) Background:

    I am using the CD40109B as part of a signal conditioning circuit to interface between an Unit Under Test (UUT) @ 15V and a PXI digital I/O board @ 3.3V with an additional circuit for signal protection inserted (this additional circuit has an ~ 560 ohm impedance).

    So, since these parts of the system are mounted in different locations, I will have ~ 2 meters of shielded twisted pair cable to pass the signal from the PXI-to-Sig.Prot.Ckt-to-Sig.Cond.Ckt (3.3V to 15V) or from Sig.Cond.Ckt(15V to 3.3V)-to-Sig.Prot.Ckt-PXI, depending on whether the channel is DI or DO.

    Therefore trying to design conservatively, I was wanting to use the RC network to filter out any stray noise picked up on the long wire runs that might induce false edges or pulses. So, I calculated that I would use an RC time constant of 450nS to filter out anything over ~ 500 kHz (I have a limited understanding of the filter theory/calculations, so I am "roughing" it a bit).

    Question:

    By following your link, I found the App Note Implications of Slow or Floating CMOS Inputs. In the "Slow Input Edge Rate" section (at the bottom of page 3) the article echoes your recommendation, stating:

    ... Therefore, the maximum input transition time of the device should not be violated, so no damage to the circuit or the package occurs.

    and then for the formula (2) (on page 6), it directs the reader to refer to the:

    maximum input rise time as specified in the data sheets

    Unfortunately, I don't see/recognize these maximum input transition or rise time values documented in the current CD40109B datasheet. It does contain Transition Time, tTHL, tTLH specifications, but it appears to me that these are for the output.  Can you help me interpret the data provided, or in some other fashion determine the slowest input rise/fall times allowed?

    b) As mentioned in the Background in question a), I need to level shift from 3.3V to 15V and also from 15V to 3.3V. Slowing down to read the CD40109B spec more closely, I see Fig.10 shows a "Recommended Operating Boundary" which does not include the (VCC=15V, VDD=3.3V) point. To me, the word "Recommended" indicates that there might be some issues or performance degradation when operating outside the boundary, but it does not necessarily represent the minimum/maximum allowed values. Will the CD10409B work for this 2nd part of my application? If so, is there anything I should do to use it for this level shift down, since it is outside the "Recommended Operating Boundary"?

    -James

  • Hey James,
    I'm always happy to help.

    For most CMOS parts, we do list a maximum recommended input transition rate (Δt/Δv). An example would be the SN74LVC1G08, which has the limit of 5ns/V at 5V operation. This is always listed in "Recommended Operating Conditions" -- which basically is saying that we can only guarantee the other datasheet specs will be met as long as the ROC are used.

    The CD4k family is quite old, as we've previously discussed, and I can only guess that this wasn't a big concern for Harris when they originally released the part since I don't see any limits in the datasheet. They may have assumed that the family would only be used in logic applications with fast signals.

    What they do provide is the expected output transition time, which is 200ns max for 10V to 5V translation. I would use a similar value for your design limit on the input transition rate. If you can keep the input edge 10% to 90% transition below 200ns, you'll be protected from the excessive current and oscillation issues that can occur with slower inputs. With many devices, you can exceed this significantly without problems, but I always recommend against that for the best performance.

    The entire CD4k family does work from 3V to 18V. The performance at 3V will probably be very poor - ie the output impedance will be large and the drive strength will be low. You will also see slower outputs. This is to be expected since the parts were designed for higher voltage operation. To get great performance at 3.3V, we usually have to limit parts to a newer process that can't handle over 5.5V.

    That being said - the CD40109 is the only device we have that will directly work for 15V to 3.3V translation. You will have limited data rates and drive current at the output. Another option is a resistor divider +3.3V device for the down-translation. It's not always the most ideal solution, but if you buffer the signal with Schmitt-trigger buffers and limit the inputs to 6.5V (for overshoot/spikes), then it's probably better than using CD40109 for output drive strength and overall signal integrity. The added Schmitt-trigger allows for direct filtering as well, since it takes away the input edge rate limitation.

    SN74LVC14A is a Schmitt-trigger inverter that's commonly used for that type of application.