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SN74LV1T08: LV1T Vin is powered during Vcc off condition

Part Number: SN74LV1T08


I am planning to use part from LV1T logic family (assume PN SN74LV1T08) for my design. I have a condition during which Vcc of the part is not powered but the A and B inputs are getting 3.3V and 5V signals from a different logic IC. I would like to know the following:

1. Is it okay to send the signals to A and B inputs when Vcc is not powered? By okay I mean to ask if the SN74LV1T08 will not get damaged or the Vcc pin will not backfeed.

2. If it is okay, how do I infer this information from the datasheet?

3. Also I assume that Vin pins are tri-stated or are in high impedance mode during Vcc = 0V.

Thank you

  • Hi Sam and welcome to the forums!

    The SN74LV1T08 does not have the Ioff specification in the Electrical Characteristics table, so it does not automatically isolate the output when Vcc = 0V.

    The inputs, on the other hand, can exceed Vcc without any problems.  There's an FAQ on this topic here:

    As for (3) -- CMOS input pins are always high-impedance, unless the device has positive clamping diodes (which this one does not).  The output pins are _not_ high-impedance at any time.

    If this answers your question, please click the green "this resolved my issue" button. If not, let me know and I will continue to try to help.

  • Hello Emrys,

    Thank you for answering my questions. I still need some clarification. So when the Vcc = 0V and there are inputs at A and B pins, what is output since output is not automatically isolated? My assumption is that since there is no Vcc voltage, the CMOS inputs pins for A and B inputs are high impedance. Also the output is not powered and therefore pulled low (I have a pull down resistor at the output). 

    Also is it safe to apply signals to the IC when it is not powered. By "safe" I mean will the IC get damaged? 

    Thank you,


  • Hey Sam,

    A CMOS output typically includes both an nFET and a pFET in the standard "inverter" configuration,

    and the area of concern is the parasitic diode in the pFET that leads from the output pin to Vcc -- unless some fancy design work prevents that current path from being available (ie Ioff circuitry is included in the device).

    If Vcc = 0V (ie the supply is OFF), then both MOSFETs are in cutoff, but the body diodes can still be activated. If the output is driven above Vcc, that parasitic diode will turn on and current will flow from the output to Vcc, "back-powering" the device and anything else connected to that rail.  If the current through the diode is large enough, it can damage the device.

    The absolute maximum ratings table lets us know that the diode can only handle 20mA of current before being damaged, so you would want to limit that current below 20mA.

    The inputs have a similar structure -- but the connection is to the gates (on the left of the above image). Any input signal will just be ignored if Vcc = 0V, since there's no V_ds to drive current through the input.

  • Thank you Emerys! I now understand. Thank you for the detailed explanation.