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SN74AHCT574: power dissipation

Part Number: SN74AHCT574



Please tell me how to calculate the power dissipation(mW) of this device.

best regrads

  • You have to combine ICC and Cpd; see CMOS Power Consumption and Cpd Calculation (SCAA035).

  • Hi, Ladisch san

    Thank you for the information.

    Please let me confirm in addition.
    Power dissipation (Pd) is not described in the absolute maximum ratings of the data sheet.
    Please tell me the Power dissipation (absolute maximum(Pd)) value as a device.

    best regards

  • HI,

    I thought as follows, is it wrong?

    The allowable loss of PKG at Ta=25℃ is
    When Rθja = 79.4℃/W of DW PKG,
    At Ta=25℃, it is recommended that Ta (max is 125℃, so a rise up to 100℃ is considered acceptable.

    (125-25)/79.4 = about 1.259 W, which is the power dissipation at DW-25℃ of DW PKG.

    The allowable loss at Ta = 100℃ is
    (125-100) / 79.4 = about 315mW
    It will be.

    Is the above idea OK?

    best regards


  • Yes, this is the correct way to calculate the maximum power dissipation.

    (At 5 V, and with all eight gates switching, the SN74AHCT574 dissipates 5.6 mW per MHz. In general, logic devices are not limited by their own operation.)