Other Parts Discussed in Thread: SN74HCS08-Q1
Hello,
The maximum recommended input transition rise or fall rate from the device SN74AHCT08Q-Q1 is 20 ns/V. In my setup in getting a rising time of from 10% to 90% of VCC around 150 ns, that means =~38 ns input transition rise. This timing value i cannot make it smaller, since it comes from a gate driver device. It is written in the application note that this could lead to oscillations at the output and i could use a Schmitt trigger to before, but it is necessary two of then and also it will impact in cost.
I would like to know, if this input transition rise must be really so strictly taken in care in the circuit design?
Thanks in Advance,
Tobias Fernandes